anv: Add fake graphics-only and compute-only queue families
Rework: * Jordan: Add graphics-only queue * Jordan: Bump ANV_MAX_QUEUE_FAMILIES and add related asserts * Jordan: Fix queueCount on compute-only family Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8771>
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@@ -483,21 +483,40 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
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uint32_t family_count = 0;
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uint32_t family_count = 0;
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if (pdevice->engine_info) {
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if (pdevice->engine_info) {
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int render_count = anv_gem_count_engines(pdevice->engine_info,
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int gc_count =
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I915_ENGINE_CLASS_RENDER);
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anv_gem_count_engines(pdevice->engine_info, I915_ENGINE_CLASS_RENDER);
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if (render_count > 0) {
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int g_count = 0;
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int c_count = 0;
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if (gc_count > 0) {
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pdevice->queue.families[family_count++] = (struct anv_queue_family) {
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pdevice->queue.families[family_count++] = (struct anv_queue_family) {
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.queueFlags = VK_QUEUE_GRAPHICS_BIT |
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.queueFlags = VK_QUEUE_GRAPHICS_BIT |
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VK_QUEUE_COMPUTE_BIT |
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VK_QUEUE_COMPUTE_BIT |
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VK_QUEUE_TRANSFER_BIT,
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VK_QUEUE_TRANSFER_BIT,
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.queueCount = render_count,
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.queueCount = gc_count,
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.engine_class = I915_ENGINE_CLASS_RENDER,
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};
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}
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if (g_count > 0) {
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pdevice->queue.families[family_count++] = (struct anv_queue_family) {
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.queueFlags = VK_QUEUE_GRAPHICS_BIT |
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VK_QUEUE_TRANSFER_BIT,
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.queueCount = g_count,
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.engine_class = I915_ENGINE_CLASS_RENDER,
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};
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}
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if (c_count > 0) {
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pdevice->queue.families[family_count++] = (struct anv_queue_family) {
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.queueFlags = VK_QUEUE_COMPUTE_BIT |
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VK_QUEUE_TRANSFER_BIT,
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.queueCount = c_count,
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.engine_class = I915_ENGINE_CLASS_RENDER,
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.engine_class = I915_ENGINE_CLASS_RENDER,
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};
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};
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}
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}
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/* Increase count below when other families are added as a reminder to
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/* Increase count below when other families are added as a reminder to
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* increase the ANV_MAX_QUEUE_FAMILIES value.
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* increase the ANV_MAX_QUEUE_FAMILIES value.
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*/
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*/
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STATIC_ASSERT(ANV_MAX_QUEUE_FAMILIES >= 1);
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STATIC_ASSERT(ANV_MAX_QUEUE_FAMILIES >= 3);
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} else {
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} else {
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/* Default to a single render queue */
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/* Default to a single render queue */
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pdevice->queue.families[family_count++] = (struct anv_queue_family) {
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pdevice->queue.families[family_count++] = (struct anv_queue_family) {
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@@ -941,7 +941,7 @@ struct anv_queue_family {
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enum drm_i915_gem_engine_class engine_class;
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enum drm_i915_gem_engine_class engine_class;
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};
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};
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#define ANV_MAX_QUEUE_FAMILIES 1
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#define ANV_MAX_QUEUE_FAMILIES 3
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struct anv_memory_type {
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struct anv_memory_type {
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/* Standard bits passed on to the client */
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/* Standard bits passed on to the client */
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