diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 80aad8f520b..930aaeac85b 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -275,12 +275,6 @@ public: unsigned *out_pull_index); void invalidate_analysis(brw::analysis_dependency_class c); -#ifndef NDEBUG - void validate(); -#else - void validate() {} -#endif - instruction_scheduler *prepare_scheduler(void *mem_ctx); void schedule_instructions_pre_ra(instruction_scheduler *sched, instruction_scheduler_mode mode); @@ -589,6 +583,12 @@ int brw_get_subgroup_id_param_index(const intel_device_info *devinfo, void nir_to_brw(fs_visitor *s); +#ifndef NDEBUG +void brw_fs_validate(const fs_visitor &s); +#else +static inline void brw_fs_validate(const fs_visitor &s) {} +#endif + void brw_fs_optimize(fs_visitor &s); bool brw_fs_lower_3src_null_dest(fs_visitor &s); diff --git a/src/intel/compiler/brw_fs_opt.cpp b/src/intel/compiler/brw_fs_opt.cpp index 9fad9a3cc27..0b81b7b5e7c 100644 --- a/src/intel/compiler/brw_fs_opt.cpp +++ b/src/intel/compiler/brw_fs_opt.cpp @@ -17,7 +17,7 @@ brw_fs_optimize(fs_visitor &s) s.debug_optimizer(nir, "start", 0, 0); /* Start by validating the shader we currently have. */ - s.validate(); + brw_fs_validate(s); bool progress = false; int iteration = 0; @@ -30,7 +30,7 @@ brw_fs_optimize(fs_visitor &s) if (this_progress) \ s.debug_optimizer(nir, #pass, iteration, pass_num); \ \ - s.validate(); \ + brw_fs_validate(s); \ \ progress = progress || this_progress; \ this_progress; \ diff --git a/src/intel/compiler/brw_fs_validate.cpp b/src/intel/compiler/brw_fs_validate.cpp index 59f6ee89195..d3e08926990 100644 --- a/src/intel/compiler/brw_fs_validate.cpp +++ b/src/intel/compiler/brw_fs_validate.cpp @@ -34,8 +34,8 @@ { \ if (!(assertion)) { \ fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \ - _mesa_shader_stage_to_abbrev(stage)); \ - dump_instruction(inst, stderr); \ + _mesa_shader_stage_to_abbrev(s.stage)); \ + s.dump_instruction(inst, stderr); \ fprintf(stderr, "%s:%d: '%s' failed\n", __FILE__, __LINE__, #assertion); \ abort(); \ } \ @@ -47,8 +47,8 @@ unsigned b = (B); \ if (a != b) { \ fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \ - _mesa_shader_stage_to_abbrev(stage)); \ - dump_instruction(inst, stderr); \ + _mesa_shader_stage_to_abbrev(s.stage)); \ + s.dump_instruction(inst, stderr); \ fprintf(stderr, "%s:%d: A == B failed\n", __FILE__, __LINE__); \ fprintf(stderr, " A = %s = %u\n", #A, a); \ fprintf(stderr, " B = %s = %u\n", #B, b); \ @@ -62,8 +62,8 @@ unsigned b = (B); \ if (a == b) { \ fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \ - _mesa_shader_stage_to_abbrev(stage)); \ - dump_instruction(inst, stderr); \ + _mesa_shader_stage_to_abbrev(s.stage)); \ + s.dump_instruction(inst, stderr); \ fprintf(stderr, "%s:%d: A != B failed\n", __FILE__, __LINE__); \ fprintf(stderr, " A = %s = %u\n", #A, a); \ fprintf(stderr, " B = %s = %u\n", #B, b); \ @@ -77,8 +77,8 @@ unsigned b = (B); \ if (a > b) { \ fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", \ - _mesa_shader_stage_to_abbrev(stage)); \ - dump_instruction(inst, stderr); \ + _mesa_shader_stage_to_abbrev(s.stage)); \ + s.dump_instruction(inst, stderr); \ fprintf(stderr, "%s:%d: A <= B failed\n", __FILE__, __LINE__); \ fprintf(stderr, " A = %s = %u\n", #A, a); \ fprintf(stderr, " B = %s = %u\n", #B, b); \ @@ -88,11 +88,13 @@ #ifndef NDEBUG void -fs_visitor::validate() +brw_fs_validate(const fs_visitor &s) { - cfg->validate(_mesa_shader_stage_to_abbrev(stage)); + const intel_device_info *devinfo = s.devinfo; - foreach_block_and_inst (block, fs_inst, inst, cfg) { + s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage)); + + foreach_block_and_inst (block, fs_inst, inst, s.cfg) { switch (inst->opcode) { case SHADER_OPCODE_SEND: fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1])); @@ -106,7 +108,7 @@ fs_visitor::validate() break; } - if (inst->is_3src(compiler)) { + if (inst->is_3src(s.compiler)) { const unsigned integer_sources = brw_reg_type_is_integer(inst->src[0].type) + brw_reg_type_is_integer(inst->src[1].type) + @@ -144,7 +146,7 @@ fs_visitor::validate() break; } } - } else if (grf_used != 0) { + } else if (s.grf_used != 0) { /* Only perform the pre-Gfx10 checks after register allocation has * occured. * @@ -174,13 +176,13 @@ fs_visitor::validate() if (inst->dst.file == VGRF) { fsv_assert_lte(inst->dst.offset / REG_SIZE + regs_written(inst), - alloc.sizes[inst->dst.nr]); + s.alloc.sizes[inst->dst.nr]); } for (unsigned i = 0; i < inst->sources; i++) { if (inst->src[i].file == VGRF) { fsv_assert_lte(inst->src[i].offset / REG_SIZE + regs_read(inst, i), - alloc.sizes[inst->src[i].nr]); + s.alloc.sizes[inst->src[i].nr]); } } diff --git a/src/intel/compiler/test_fs_combine_constants.cpp b/src/intel/compiler/test_fs_combine_constants.cpp index d67e5a3e9db..4094d548c09 100644 --- a/src/intel/compiler/test_fs_combine_constants.cpp +++ b/src/intel/compiler/test_fs_combine_constants.cpp @@ -125,6 +125,6 @@ TEST_F(FSCombineConstantsTest, DoContainingDo) * test is that the shader would be empty. */ ASSERT_GE(shader->cfg->num_blocks, original_num_blocks); - shader->validate(); + brw_fs_validate(*shader); }