From 12becb8839a6fb3a1b5c82aeddb7340fbb3786fb Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 28 Sep 2022 17:17:35 +0100 Subject: [PATCH] radv: lower streamout in NIR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Timur Kristóf Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 3 --- src/amd/vulkan/radv_nir_to_llvm.c | 6 ------ src/amd/vulkan/radv_pipeline.c | 2 +- 3 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index d1b57b15d20..a9a63aa0506 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -12095,9 +12095,6 @@ select_program(Program* program, unsigned shader_count, struct nir_shader* const visit_cf_list(&ctx, &func->body); - if (ctx.program->info.so.num_outputs && ctx.stage.hw == HWStage::VS) - emit_streamout(&ctx, 0); - if (nir->info.stage == MESA_SHADER_GEOMETRY && !ngg_gs) { Builder bld(ctx.program, ctx.block); bld.barrier(aco_opcode::p_barrier, diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 0404d030a52..588ab195c8c 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1018,12 +1018,6 @@ handle_vs_outputs_post(struct radv_shader_context *ctx) struct radv_shader_output_values *outputs; unsigned noutput = 0; - if (ctx->shader_info->so.num_outputs && !ctx->args->is_gs_copy_shader && - ctx->stage != MESA_SHADER_GEOMETRY && !ctx->shader_info->is_ngg) { - /* The GS copy shader emission already emits streamout. */ - radv_emit_streamout(ctx, 0); - } - /* Allocate a temporary array for the output values. */ unsigned num_outputs = util_bitcount64(ctx->output_mask); outputs = malloc(num_outputs * sizeof(outputs[0])); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 90c109ee238..eff0661deea 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3850,7 +3850,7 @@ radv_postprocess_nir(struct radv_pipeline *pipeline, if (stage->stage == last_vgt_api_stage && stage->stage != MESA_SHADER_GEOMETRY && !lowered_ngg) NIR_PASS_V(stage->nir, ac_nir_lower_legacy_vs, - stage->info.outinfo.export_prim_id ? VARYING_SLOT_PRIMITIVE_ID : -1, true); + stage->info.outinfo.export_prim_id ? VARYING_SLOT_PRIMITIVE_ID : -1, false); NIR_PASS(_, stage->nir, nir_opt_idiv_const, 8);