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intel: Collapse is_ssa checks

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
This commit is contained in:
Alyssa Rosenzweig
2023-08-01 12:24:31 -04:00
committed by Marge Bot
parent cf8ceb6e0a
commit 11fc4f969c
5 changed files with 28 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -4067,10 +4067,7 @@ fs_visitor::try_rebuild_resource(const brw::fs_builder &bld, nir_ssa_def *resour
if (nir_op_infos[alu->op].num_inputs != 2) if (nir_op_infos[alu->op].num_inputs != 2)
break; break;
if (!alu->src[0].src.is_ssa || if (alu->src[0].swizzle[0] != 0 || alu->src[1].swizzle[0] != 0)
!alu->src[1].src.is_ssa ||
alu->src[0].swizzle[0] != 0 ||
alu->src[1].swizzle[0] != 0)
break; break;
switch (alu->op) { switch (alu->op) {

16
src/intel/compiler/brw_mesh.cpp
View File

@@ -1893,15 +1893,13 @@ fs_visitor::emit_task_mesh_store(const fs_builder &bld, nir_intrinsic_instr *ins
bool use_mod = false; bool use_mod = false;
unsigned mod; unsigned mod;
if (offset_nir_src->is_ssa) { /* Try to calculate the value of (offset + base) % 4. If we can do
/* Try to calculate the value of (offset + base) % 4. If we can do * this, then we can do indirect writes using only 1 URB write.
* this, then we can do indirect writes using only 1 URB write. */
*/ use_mod = nir_mod_analysis(nir_get_ssa_scalar(offset_nir_src->ssa, 0), nir_type_uint, 4, &mod);
use_mod = nir_mod_analysis(nir_get_ssa_scalar(offset_nir_src->ssa, 0), nir_type_uint, 4, &mod); if (use_mod) {
if (use_mod) { mod += nir_intrinsic_base(instr) + component_from_intrinsic(instr);
mod += nir_intrinsic_base(instr) + component_from_intrinsic(instr); mod %= 4;
mod %= 4;
}
} }
if (use_mod) { if (use_mod) {

2
src/intel/compiler/brw_nir.h
View File

@@ -116,7 +116,7 @@ struct brw_nir_compiler_opts {
static inline bool static inline bool
brw_nir_ubo_surface_index_is_pushable(nir_src src) brw_nir_ubo_surface_index_is_pushable(nir_src src)
{ {
nir_intrinsic_instr *intrin = src.is_ssa && nir_intrinsic_instr *intrin =
src.ssa->parent_instr->type == nir_instr_type_intrinsic ? src.ssa->parent_instr->type == nir_instr_type_intrinsic ?
nir_instr_as_intrinsic(src.ssa->parent_instr) : NULL; nir_instr_as_intrinsic(src.ssa->parent_instr) : NULL;

49
src/intel/compiler/brw_nir_analyze_boolean_resolves.c
View File

@@ -40,19 +40,15 @@
static uint8_t static uint8_t
get_resolve_status_for_src(nir_src *src) get_resolve_status_for_src(nir_src *src)
{ {
if (src->is_ssa) { nir_instr *src_instr = src->ssa->parent_instr;
nir_instr *src_instr = src->ssa->parent_instr; uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK;
uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK;
/* If the source instruction needs resolve, then from the perspective /* If the source instruction needs resolve, then from the perspective
* of the user, it's a true boolean. * of the user, it's a true boolean.
*/ */
if (resolve_status == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) if (resolve_status == BRW_NIR_BOOLEAN_NEEDS_RESOLVE)
resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE; resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE;
return resolve_status; return resolve_status;
} else {
return BRW_NIR_NON_BOOLEAN;
}
} }
/** Marks the given source as needing a resolve /** Marks the given source as needing a resolve
@@ -63,18 +59,15 @@ get_resolve_status_for_src(nir_src *src)
static bool static bool
src_mark_needs_resolve(nir_src *src, void *void_state) src_mark_needs_resolve(nir_src *src, void *void_state)
{ {
if (src->is_ssa) { nir_instr *src_instr = src->ssa->parent_instr;
nir_instr *src_instr = src->ssa->parent_instr; uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK;
uint8_t resolve_status = src_instr->pass_flags & BRW_NIR_BOOLEAN_MASK;
/* If the source instruction is unresolved, then mark it as needing
* to be resolved.
*/
if (resolve_status == BRW_NIR_BOOLEAN_UNRESOLVED) {
src_instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK;
src_instr->pass_flags |= BRW_NIR_BOOLEAN_NEEDS_RESOLVE;
}
/* If the source instruction is unresolved, then mark it as needing
* to be resolved.
*/
if (resolve_status == BRW_NIR_BOOLEAN_UNRESOLVED) {
src_instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK;
src_instr->pass_flags |= BRW_NIR_BOOLEAN_NEEDS_RESOLVE;
} }
return true; return true;
@@ -187,15 +180,7 @@ analyze_boolean_resolves_block(nir_block *block)
} }
} }
/* If the destination is SSA, go ahead allow unresolved booleans. /* Go ahead allow unresolved booleans. */
* If the destination register doesn't have a well-defined parent_instr
* we need to resolve immediately.
*/
if (!alu->dest.dest.is_ssa &&
resolve_status == BRW_NIR_BOOLEAN_UNRESOLVED) {
resolve_status = BRW_NIR_BOOLEAN_NEEDS_RESOLVE;
}
instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) | instr->pass_flags = (instr->pass_flags & ~BRW_NIR_BOOLEAN_MASK) |
resolve_status; resolve_status;

8
src/intel/compiler/brw_vec4_nir.cpp
View File

@@ -792,8 +792,7 @@ bool
vec4_visitor::optimize_predicate(nir_alu_instr *instr, vec4_visitor::optimize_predicate(nir_alu_instr *instr,
enum brw_predicate *predicate) enum brw_predicate *predicate)
{ {
if (!instr->src[0].src.is_ssa || if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
return false; return false;
nir_alu_instr *cmp_instr = nir_alu_instr *cmp_instr =
@@ -1327,10 +1326,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_fceil: { case nir_op_fceil: {
src_reg tmp = src_reg(this, glsl_type::float_type); src_reg tmp = src_reg(this, glsl_type::float_type);
tmp.swizzle = tmp.swizzle = brw_swizzle_for_size(nir_src_num_components(instr->src[0].src));
brw_swizzle_for_size(instr->src[0].src.is_ssa ?
instr->src[0].src.ssa->num_components :
instr->src[0].src.reg.reg->num_components);
op[0].negate = !op[0].negate; op[0].negate = !op[0].negate;
emit(RNDD(dst_reg(tmp), op[0])); emit(RNDD(dst_reg(tmp), op[0]));