i965: Create a new fragment shader backend for Broadwell.

This replaces the old fs_generator backend.

v2: Port to the C-based representation of assembly instructions.
    Fix texturing after the texture-grf merge.

v3: Add high quality derivative support.  Fix SET_SIMD4X2_OFFSET.

v4: Pass brw_context to gen8_instruction functions as required.

v5: Fixes for MRT, as well as zero render targets (alpha test only).

v6: Replace n-wide with SIMDn in comments and messages; port over
    Topi's blorp-generator changes; add missing TXF_MCS opcode,
    fix missing high quality derivatives for DDX; fix typo (all caught
    by Eric).  Simplify ADDC/SUBB handling; drop "Used only on Gen6+"
    comment (caught by Matt).  Emit SIMD16 versions of three source
    instructions (caught by both Eric and Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

src/mesa/drivers/dri/i965/Makefile.sources

@@ -140,6 +140,7 @@ i965_FILES = \
 	gen7_wm_state.c \
 	gen7_wm_surface_state.c \
 	gen8_disasm.c \
+	gen8_fs_generator.cpp \
 	gen8_generator.cpp \
 	gen8_instruction.c \
 	gen8_vec4_generator.cpp \

src/mesa/drivers/dri/i965/brw_fs.cpp

@@ -3346,10 +3346,16 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
       }
    }
 
-   fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
-   const unsigned *generated = g.generate_assembly(&v.instructions,
-                                                   simd16_instructions,
-                                                   final_assembly_size);
+   const unsigned *assembly = NULL;
+   if (brw->gen >= 8) {
+      gen8_fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
+      assembly = g.generate_assembly(&v.instructions, simd16_instructions,
+                                     final_assembly_size);
+   } else {
+      fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
+      assembly = g.generate_assembly(&v.instructions, simd16_instructions,
+                                     final_assembly_size);
+   }
 
    if (unlikely(brw->perf_debug) && shader) {
       if (shader->compiled_once)
@@ -3362,7 +3368,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
       }
    }
 
-   return generated;
+   return assembly;
 }
 
 bool

src/mesa/drivers/dri/i965/brw_fs.h

@@ -47,6 +47,7 @@ extern "C" {
 #include "brw_wm.h"
 #include "brw_shader.h"
 }
+#include "gen8_generator.h"
 #include "glsl/glsl_types.h"
 #include "glsl/ir.h"
 
@@ -618,6 +619,68 @@ private:
    void *mem_ctx;
 };
 
+/**
+ * The fragment shader code generator.
+ *
+ * Translates FS IR to actual i965 assembly code.
+ */
+class gen8_fs_generator : public gen8_generator
+{
+public:
+   gen8_fs_generator(struct brw_context *brw,
+                     struct brw_wm_compile *c,
+                     struct gl_shader_program *prog,
+                     struct gl_fragment_program *fp,
+                     bool dual_source_output);
+   ~gen8_fs_generator();
+
+   const unsigned *generate_assembly(exec_list *simd8_instructions,
+                                     exec_list *simd16_instructions,
+                                     unsigned *assembly_size);
+
+private:
+   void generate_code(exec_list *instructions);
+   void generate_fb_write(fs_inst *inst);
+   void generate_linterp(fs_inst *inst, struct brw_reg dst,
+                         struct brw_reg *src);
+   void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_math2(fs_inst *inst, struct brw_reg dst,
+                       struct brw_reg src0, struct brw_reg src1);
+   void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+                     bool negate_value);
+   void generate_scratch_write(fs_inst *inst, struct brw_reg src);
+   void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
+   void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
+   void generate_uniform_pull_constant_load(fs_inst *inst,
+                                            struct brw_reg dst,
+                                            struct brw_reg index,
+                                            struct brw_reg offset);
+   void generate_varying_pull_constant_load(fs_inst *inst,
+                                            struct brw_reg dst,
+                                            struct brw_reg index,
+                                            struct brw_reg offset);
+   void generate_mov_dispatch_to_flags(fs_inst *ir);
+   void generate_set_simd4x2_offset(fs_inst *ir,
+                                    struct brw_reg dst,
+                                    struct brw_reg offset);
+   void generate_discard_jump(fs_inst *ir);
+
+   void patch_discard_jumps_to_fb_writes();
+
+   void mark_surface_used(unsigned surf_index);
+
+   struct brw_wm_compile *c;
+   const struct gl_fragment_program *fp;
+
+   unsigned dispatch_width; /** 8 or 16 */
+
+   bool dual_source_output;
+
+   exec_list discard_halt_patches;
+};
+
 bool brw_do_channel_expressions(struct exec_list *instructions);
 bool brw_do_vector_splitting(struct exec_list *instructions);
 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);