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broadcom/compiler: avoid using ldvary sequence to hide latency of branching

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This can cause us to stomp the contents of r5 before we have a chance to read
it, like this:

0x3d103186bb800000 nop                           ; nop                         ; ldvary.r0
0x3d105686bbf40000 nop                           ; mov rf26, r5                ; ldvary.r1
0x020000ef0000d000 bu.allna  232, r:unif (0x0000001c / 0.000000)
0x3d1096c6bbf40000 nop                           ; mov rf27, r5                ; ldvary.r2

Here, the MOV in the last instruction is supposed to read r5 produced from
ldvary.r0, but because we have inserted the bu instruction in between now
that read happens at the same time that ldvary.r1 updates r5, stomping the
value we were supposed to read.

Fix this by disallowing injection of a branch instruction in between an ldvary
instruction and its write to the r5 register 2 instructions later.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7062
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19616>
This commit is contained in:
Iago Toral Quiroga
2022-11-09 13:07:45 +01:00
committed by Marge Bot
parent 019ca611fa
commit 1174f37609
1 changed files with 8 additions and 0 deletions
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8
src/broadcom/compiler/qpu_schedule.c
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@@ -1953,6 +1953,14 @@ emit_branch(struct v3d_compile *c,
break;
}
/* Do not move up a branch if it can disrupt an ldvary sequence
* as that can cause stomping of the r5 register.
*/
if (scoreboard->last_ldvary_tick + 2 >=
branch_tick - slots_filled) {
break;
}
/* Can't move a conditional branch before the instruction
* that writes the flags for its condition.
*/