agx: Allow drivers to lower texture handles
Rather than hardcoding u0_u1, this lets drivers map texture handles in whatever way is convenient. In particular, this makes textures work properly with merged shader stages (provided one of the stages is forced to use bindless access), by giving each stage an independent texture heap. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26056>
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@@ -15,6 +15,7 @@
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#include "agx_debug.h"
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#include "agx_internal_formats.h"
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#include "agx_nir.h"
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#include "nir.h"
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#include "nir_intrinsics.h"
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/* Alignment for shader programs. I'm not sure what the optimal value is. */
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@@ -2629,6 +2630,27 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *_)
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return 0;
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}
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static bool
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lower_load_from_texture_handle(nir_builder *b, nir_intrinsic_instr *intr,
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void *data)
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{
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if (intr->intrinsic != nir_intrinsic_load_from_texture_handle_agx)
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return false;
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/* Bindless handles are a vec2, where the first source is the (constant)
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* uniform register number and the second source is the byte offset.
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*/
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nir_scalar uniform = nir_scalar_resolved(intr->src[0].ssa, 0);
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unsigned uniform_idx = nir_scalar_as_uint(uniform);
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b->cursor = nir_instr_remove(&intr->instr);
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nir_def *base = nir_load_preamble(b, 1, 64, uniform_idx);
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nir_def *offset = nir_u2u64(b, nir_channel(b, intr->src[0].ssa, 1));
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nir_def_rewrite_uses(&intr->def, nir_iadd(b, base, offset));
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return true;
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}
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static bool
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agx_should_dump(nir_shader *nir, unsigned agx_dbg_bit)
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{
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@@ -2956,6 +2978,10 @@ agx_compile_shader_nir(nir_shader *nir, struct agx_shader_key *key,
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NIR_PASS_V(nir, agx_nir_lower_layer);
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}
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NIR_PASS_V(nir, nir_opt_constant_folding);
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NIR_PASS_V(nir, nir_shader_intrinsics_pass, lower_load_from_texture_handle,
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nir_metadata_block_index | nir_metadata_dominance, NULL);
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out->push_count = key->reserved_preamble;
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agx_optimize_nir(nir, &out->push_count);
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