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nir,ac/llvm: add nir_intrinsic_load_ordered_id_amd

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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
This commit is contained in:
Qiang Yu
2022-06-30 17:56:50 +08:00
committed by Marge Bot
parent 5c2d710064
commit 1119e06a45
3 changed files with 7 additions and 0 deletions
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3
src/amd/llvm/ac_nir_to_llvm.c
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@@ -3616,6 +3616,9 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_load_user_clip_plane: case nir_intrinsic_load_user_clip_plane:
result = ctx->abi->load_user_clip_plane(ctx->abi, nir_intrinsic_ucp_id(instr)); result = ctx->abi->load_user_clip_plane(ctx->abi, nir_intrinsic_ucp_id(instr));
break; break;
case nir_intrinsic_load_ordered_id_amd:
result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info), 0, 12);
break;
case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_vertex_id_zero_base:
result = ctx->abi->vertex_id_replaced ? ctx->abi->vertex_id_replaced : ctx->abi->vertex_id; result = ctx->abi->vertex_id_replaced ? ctx->abi->vertex_id_replaced : ctx->abi->vertex_id;
break; break;

1
src/compiler/nir/nir_divergence_analysis.c
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@@ -185,6 +185,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_clip_half_line_width_amd: case nir_intrinsic_load_clip_half_line_width_amd:
case nir_intrinsic_load_num_vertices_per_primitive_amd: case nir_intrinsic_load_num_vertices_per_primitive_amd:
case nir_intrinsic_load_streamout_buffer_amd: case nir_intrinsic_load_streamout_buffer_amd:
case nir_intrinsic_load_ordered_id_amd:
is_divergent = false; is_divergent = false;
break; break;

3
src/compiler/nir/nir_intrinsics.py
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@@ -1431,6 +1431,9 @@ system_value("num_vertices_per_primitive_amd", 1)
# BASE = buffer index # BASE = buffer index
intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER])
# An ID for each workgroup ordered by primitve sequence
system_value("ordered_id_amd", 1)
# V3D-specific instrinc for tile buffer color reads. # V3D-specific instrinc for tile buffer color reads.
# #
# The hardware requires that we read the samples and components of a pixel # The hardware requires that we read the samples and components of a pixel