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gallium/radeon: drop support for LLVM 3.5

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

v2: adjust the comment in the amdgpu winsys
This commit is contained in:
Marek Olšák
2016-02-10 21:48:59 +01:00
parent 3dc1cb0cc7
commit 100796c15c
9 changed files with 11 additions and 186 deletions
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2
configure.ac
View File

@@ -2186,7 +2186,7 @@ radeon_llvm_check() {
if test "x$enable_gallium_llvm" != "xyes"; then
AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
fi
llvm_check_version_for "3" "5" "0" $1
llvm_check_version_for "3" "6" "0" $1
if test true && $LLVM_CONFIG --targets-built | grep -iqvw $amdgpu_llvm_target_name ; then
AC_MSG_ERROR([LLVM $amdgpu_llvm_target_name not enabled in your LLVM build.])
fi

75
src/gallium/drivers/r600/evergreen_compute.c
View File

@@ -208,23 +208,6 @@ void *evergreen_create_compute_state(
COMPUTE_DBG(ctx->screen, "*** evergreen_create_compute_state\n");
header = cso->prog;
code = cso->prog + sizeof(struct pipe_llvm_program_header);
#if HAVE_LLVM < 0x0306
(void)use_kill;
(void)p;
shader->llvm_ctx = LLVMContextCreate();
shader->num_kernels = radeon_llvm_get_num_kernels(shader->llvm_ctx,
code, header->num_bytes);
shader->kernels = CALLOC(sizeof(struct r600_kernel),
shader->num_kernels);
{
unsigned i;
for (i = 0; i < shader->num_kernels; i++) {
struct r600_kernel *kernel = &shader->kernels[i];
kernel->llvm_module = radeon_llvm_get_kernel_module(
shader->llvm_ctx, i, code, header->num_bytes);
}
}
#else
radeon_shader_binary_init(&shader->binary);
radeon_elf_read(code, header->num_bytes, &shader->binary);
r600_create_shader(&shader->bc, &shader->binary, &use_kill);
@@ -234,7 +217,6 @@ void *evergreen_create_compute_state(
p = r600_buffer_map_sync_with_rings(&ctx->b, shader->code_bo, PIPE_TRANSFER_WRITE);
memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4);
ctx->b.ws->buffer_unmap(shader->code_bo->buf);
#endif
#endif
shader->ctx = ctx;
@@ -255,20 +237,11 @@ void evergreen_delete_compute_state(struct pipe_context *ctx_, void* state)
return;
#ifdef HAVE_OPENCL
#if HAVE_LLVM < 0x0306
for (unsigned i = 0; i < shader->num_kernels; i++) {
struct r600_kernel *kernel = &shader->kernels[i];
LLVMDisposeModule(module);
}
FREE(shader->kernels);
LLVMContextDispose(shader->llvm_ctx);
#else
radeon_shader_binary_clean(&shader->binary);
r600_destroy_shader(&shader->bc);
/* TODO destroy shader->code_bo, shader->const_bo
* we'll need something like r600_buffer_free */
#endif
#endif
FREE(shader);
}
@@ -372,11 +345,7 @@ static void evergreen_emit_direct_dispatch(
int group_size = 1;
int grid_size = 1;
unsigned lds_size = shader->local_size / 4 +
#if HAVE_LLVM < 0x0306
shader->active_kernel->bc.nlds_dw;
#else
shader->bc.nlds_dw;
#endif
/* Calculate group_size/grid_size */
@@ -565,18 +534,10 @@ void evergreen_emit_cs_shader(
struct r600_resource *code_bo;
unsigned ngpr, nstack;
#if HAVE_LLVM < 0x0306
struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
code_bo = kernel->code_bo;
va = kernel->code_bo->gpu_address;
ngpr = kernel->bc.ngpr;
nstack = kernel->bc.nstack;
#else
code_bo = shader->code_bo;
va = shader->code_bo->gpu_address + state->pc;
ngpr = shader->bc.ngpr;
nstack = shader->bc.nstack;
#endif
radeon_compute_set_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
@@ -601,45 +562,9 @@ static void evergreen_launch_grid(
struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
boolean use_kill;
#if HAVE_LLVM < 0x0306
struct r600_kernel *kernel = &shader->kernels[pc];
(void)use_kill;
if (!kernel->code_bo) {
void *p;
struct r600_bytecode *bc = &kernel->bc;
LLVMModuleRef mod = kernel->llvm_module;
boolean use_kill = false;
bool dump = (ctx->screen->b.debug_flags & DBG_CS) != 0;
unsigned use_sb = ctx->screen->b.debug_flags & DBG_SB_CS;
unsigned sb_disasm = use_sb ||
(ctx->screen->b.debug_flags & DBG_SB_DISASM);
r600_bytecode_init(bc, ctx->b.chip_class, ctx->b.family,
ctx->screen->has_compressed_msaa_texturing);
bc->type = TGSI_PROCESSOR_COMPUTE;
bc->isa = ctx->isa;
r600_llvm_compile(mod, ctx->b.family, bc, &use_kill, dump, &ctx->b.debug);
if (dump && !sb_disasm) {
r600_bytecode_disasm(bc);
} else if ((dump && sb_disasm) || use_sb) {
if (r600_sb_bytecode_process(ctx, bc, NULL, dump, use_sb))
R600_ERR("r600_sb_bytecode_process failed!\n");
}
kernel->code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
kernel->bc.ndw * 4);
p = r600_buffer_map_sync_with_rings(&ctx->b, kernel->code_bo, PIPE_TRANSFER_WRITE);
memcpy(p, kernel->bc.bytecode, kernel->bc.ndw * 4);
ctx->b.ws->buffer_unmap(kernel->code_bo->buf);
}
shader->active_kernel = kernel;
ctx->cs_shader_state.kernel_index = pc;
#else
ctx->cs_shader_state.pc = pc;
/* Get the config information for this kernel. */
r600_shader_binary_read_config(&shader->binary, &shader->bc, pc, &use_kill);
#endif
#endif
COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", pc);

19
src/gallium/drivers/r600/evergreen_compute_internal.h
View File

@@ -27,28 +27,9 @@
#include "r600_asm.h"
#if HAVE_LLVM < 0x0306
struct r600_kernel {
unsigned count;
#ifdef HAVE_OPENCL
LLVMModuleRef llvm_module;
#endif
struct r600_resource *code_bo;
struct r600_bytecode bc;
};
#endif
struct r600_pipe_compute {
struct r600_context *ctx;
#if HAVE_LLVM < 0x0306
unsigned num_kernels;
struct r600_kernel *kernels;
struct r600_kernel *active_kernel;
#endif
struct radeon_shader_binary binary;
struct r600_resource *code_bo;
struct r600_bytecode bc;

4
src/gallium/drivers/r600/r600_pipe.c
View File

@@ -528,11 +528,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
return 16;
case PIPE_SHADER_CAP_PREFERRED_IR:
if (shader == PIPE_SHADER_COMPUTE) {
#if HAVE_LLVM < 0x0306
return PIPE_SHADER_IR_LLVM;
#else
return PIPE_SHADER_IR_NATIVE;
#endif
} else {
return PIPE_SHADER_IR_TGSI;
}

7
src/gallium/drivers/radeon/r600_pipe_common.c
View File

@@ -613,7 +613,7 @@ static int r600_get_compute_param(struct pipe_screen *screen,
case PIPE_COMPUTE_CAP_IR_TARGET: {
const char *gpu;
const char *triple;
if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
if (rscreen->family <= CHIP_ARUBA) {
triple = "r600--";
} else {
triple = "amdgcn--";
@@ -622,11 +622,6 @@ static int r600_get_compute_param(struct pipe_screen *screen,
/* Clang < 3.6 is missing Hainan in its list of
* GPUs, so we need to use the name of a similar GPU.
*/
#if HAVE_LLVM < 0x0306
case CHIP_HAINAN:
gpu = "oland";
break;
#endif
default:
gpu = r600_get_llvm_processor_name(rscreen->family);
break;

58
src/gallium/drivers/radeonsi/si_compute.c
View File

@@ -45,12 +45,6 @@ struct si_compute {
struct r600_resource *input_buffer;
struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
#if HAVE_LLVM < 0x0306
unsigned num_kernels;
struct si_shader *kernels;
LLVMContextRef llvm_ctx;
#endif
};
static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
@@ -111,29 +105,6 @@ static void *si_create_compute_state(
program->private_size = cso->req_private_mem;
program->input_size = cso->req_input_mem;
#if HAVE_LLVM < 0x0306
{
unsigned i;
program->llvm_ctx = LLVMContextCreate();
program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
code, header->num_bytes);
program->kernels = CALLOC(sizeof(struct si_shader),
program->num_kernels);
for (i = 0; i < program->num_kernels; i++) {
LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
code, header->num_bytes);
si_compile_llvm(sctx->screen, &program->kernels[i].binary,
&program->kernels[i].config, sctx->tm,
mod, &sctx->b.debug, TGSI_PROCESSOR_COMPUTE,
"Compute Shader");
si_shader_dump(sctx->screen, &program->kernels[i],
&sctx->b.debug, TGSI_PROCESSOR_COMPUTE);
si_shader_binary_upload(sctx->screen, &program->kernels[i]);
LLVMDisposeModule(mod);
}
}
#else
radeon_elf_read(code, header->num_bytes, &program->shader.binary);
/* init_scratch_buffer patches the shader code with the scratch address,
@@ -147,7 +118,6 @@ static void *si_create_compute_state(
TGSI_PROCESSOR_COMPUTE);
si_shader_binary_upload(sctx->screen, &program->shader);
#endif
program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
PIPE_USAGE_IMMUTABLE, program->input_size);
@@ -247,11 +217,6 @@ static void si_launch_grid(
unsigned lds_blocks;
unsigned num_waves_for_scratch;
#if HAVE_LLVM < 0x0306
shader = &program->kernels[pc];
#endif
radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
radeon_emit(cs, 0x80000000);
radeon_emit(cs, 0x80000000);
@@ -266,10 +231,8 @@ static void si_launch_grid(
pm4->compute_pkt = true;
#if HAVE_LLVM >= 0x0306
/* Read the config information */
si_shader_binary_read_config(&shader->binary, &shader->config, pc);
#endif
/* Upload the kernel arguments */
@@ -360,10 +323,8 @@ static void si_launch_grid(
}
shader_va = shader->bo->gpu_address;
#if HAVE_LLVM >= 0x0306
shader_va += pc;
#endif
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
@@ -448,26 +409,9 @@ static void si_delete_compute_state(struct pipe_context *ctx, void* state){
return;
}
#if HAVE_LLVM < 0x0306
if (program->kernels) {
for (int i = 0; i < program->num_kernels; i++){
if (program->kernels[i].bo){
si_shader_destroy(&program->kernels[i]);
}
}
FREE(program->kernels);
}
if (program->llvm_ctx){
LLVMContextDispose(program->llvm_ctx);
}
#else
si_shader_destroy(&program->shader);
#endif
pipe_resource_reference(
(struct pipe_resource **)&program->input_buffer, NULL);
FREE(program);
}

17
src/gallium/drivers/radeonsi/si_pipe.c
View File

@@ -74,9 +74,7 @@ static void si_destroy_context(struct pipe_context *context)
r600_common_context_cleanup(&sctx->b);
#if HAVE_LLVM >= 0x0306
LLVMDisposeTargetMachine(sctx->tm);
#endif
r600_resource_reference(&sctx->trace_buf, NULL);
r600_resource_reference(&sctx->last_trace_buf, NULL);
@@ -104,9 +102,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->b.ws;
LLVMTargetRef r600_target;
#if HAVE_LLVM >= 0x0306
const char *triple = "amdgcn--";
#endif
int shader, i;
if (!sctx)
@@ -210,7 +206,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
*/
sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
#if HAVE_LLVM >= 0x0306
/* Initialize LLVM TargetMachine */
r600_target = radeon_llvm_get_r600_target(triple);
sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
@@ -223,7 +218,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
LLVMCodeGenLevelDefault,
LLVMRelocDefault,
LLVMCodeModelDefault);
#endif
return &sctx->b.b;
fail:
@@ -310,6 +304,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -335,9 +330,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return 4;
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
return HAVE_LLVM >= 0x0306;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return HAVE_LLVM >= 0x0307 ? 410 : 330;
@@ -449,18 +441,13 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
/* LLVM 3.6.2 is required for tessellation because of bug fixes there */
if (HAVE_LLVM < 0x0306 ||
(HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2))
if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
return 0;
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
case PIPE_SHADER_CAP_PREFERRED_IR:
#if HAVE_LLVM < 0x0306
return PIPE_SHADER_IR_LLVM;
#else
return PIPE_SHADER_IR_NATIVE;
#endif
case PIPE_SHADER_CAP_DOUBLES:
return HAVE_LLVM >= 0x0307;

10
src/gallium/drivers/radeonsi/si_shader.c
View File

@@ -4374,12 +4374,10 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
if (HAVE_LLVM >= 0x0306) {
bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
}
bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
}
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,

5
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View File

@@ -174,10 +174,9 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
goto fail;
}
/* LLVM 3.6 is required for VI. */
/* LLVM 3.6.1 is required for VI. */
if (ws->info.chip_class >= VI &&
(HAVE_LLVM < 0x0306 ||
(HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) {
HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1) {
fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
goto fail;