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tu: Merge RB_DEPTH_CNTL and RB_STENCIL_CONTROL drawstates

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We're again running out of draw states, and this matches what gallium
does.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20304>
This commit is contained in:
Connor Abbott
2022-11-21 18:36:19 +01:00
committed by Marge Bot
parent 7673fcf206
commit 0f33d0392a
4 changed files with 38 additions and 48 deletions
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31
src/freedreno/vulkan/tu_cmd_buffer.cc
View File

@@ -2829,8 +2829,8 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
*/
UPDATE_REG(rast, gras_su_cntl, RAST);
UPDATE_REG(rast, gras_cl_cntl, RAST);
UPDATE_REG(rast_ds, rb_depth_cntl, RB_DEPTH_CNTL);
UPDATE_REG(ds, rb_stencil_cntl, RB_STENCIL_CNTL);
UPDATE_REG(rast_ds, rb_depth_cntl, DS);
UPDATE_REG(ds, rb_stencil_cntl, DS);
UPDATE_REG(rast, pc_raster_cntl, PC_RASTER_CNTL);
UPDATE_REG(rast, vpc_unknown_9107, PC_RASTER_CNTL);
UPDATE_REG(blend, sp_blend_cntl, BLEND);
@@ -2880,7 +2880,7 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
}
if (pipeline->output.rb_depth_cntl_disable)
cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3101,7 +3101,7 @@ tu_CmdSetDepthTestEnableEXT(VkCommandBuffer commandBuffer,
if (depthTestEnable)
cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3115,7 +3115,7 @@ tu_CmdSetDepthWriteEnableEXT(VkCommandBuffer commandBuffer,
if (depthWriteEnable)
cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3129,7 +3129,7 @@ tu_CmdSetDepthCompareOpEXT(VkCommandBuffer commandBuffer,
cmd->state.rb_depth_cntl |=
A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(depthCompareOp));
cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3143,7 +3143,7 @@ tu_CmdSetDepthBoundsTestEnableEXT(VkCommandBuffer commandBuffer,
if (depthBoundsTestEnable)
cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3164,7 +3164,7 @@ tu_CmdSetStencilTestEnableEXT(VkCommandBuffer commandBuffer,
A6XX_RB_STENCIL_CONTROL_STENCIL_READ;
}
cmd->state.dirty |= TU_CMD_DIRTY_RB_STENCIL_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3205,7 +3205,7 @@ tu_CmdSetStencilOpEXT(VkCommandBuffer commandBuffer,
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(depthFailOp));
}
cmd->state.dirty |= TU_CMD_DIRTY_RB_STENCIL_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -3346,7 +3346,7 @@ tu_CmdSetDepthClampEnableEXT(VkCommandBuffer commandBuffer,
cmd->state.rb_depth_cntl =
(cmd->state.rb_depth_cntl & ~A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE) |
COND(depthClampEnable, A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE);
cmd->state.dirty |= TU_CMD_DIRTY_RAST | TU_CMD_DIRTY_RB_DEPTH_CNTL;
cmd->state.dirty |= TU_CMD_DIRTY_RAST | TU_CMD_DIRTY_DS;
}
VKAPI_ATTR void VKAPI_CALL
@@ -4966,8 +4966,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
return VK_SUCCESS;
bool dirty_lrz =
dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL |
TU_CMD_DIRTY_RB_STENCIL_CNTL | TU_CMD_DIRTY_BLEND);
dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_DS | TU_CMD_DIRTY_BLEND);
if (dirty_lrz) {
struct tu_cs cs;
@@ -5010,8 +5009,8 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
gras_cl_cntl, cmd->state.polygon_mode);
}
if (dirty & TU_CMD_DIRTY_RB_DEPTH_CNTL) {
struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2);
if (dirty & TU_CMD_DIRTY_DS) {
struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_DS, 4);
uint32_t rb_depth_cntl = cmd->state.rb_depth_cntl;
if ((rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE) ||
@@ -5026,10 +5025,6 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
rb_depth_cntl = 0;
tu_cs_emit_regs(&cs, A6XX_RB_DEPTH_CNTL(.dword = rb_depth_cntl));
}
if (dirty & TU_CMD_DIRTY_RB_STENCIL_CNTL) {
struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2);
tu_cs_emit_regs(&cs, A6XX_RB_STENCIL_CONTROL(.dword = cmd->state.rb_stencil_cntl));
}

25
src/freedreno/vulkan/tu_cmd_buffer.h
View File

@@ -56,20 +56,19 @@ enum tu_cmd_dirty_bits
TU_CMD_DIRTY_VERTEX_BUFFERS = BIT(0),
TU_CMD_DIRTY_VB_STRIDE = BIT(1),
TU_CMD_DIRTY_RAST = BIT(2),
TU_CMD_DIRTY_RB_DEPTH_CNTL = BIT(3),
TU_CMD_DIRTY_RB_STENCIL_CNTL = BIT(4),
TU_CMD_DIRTY_DESC_SETS = BIT(5),
TU_CMD_DIRTY_COMPUTE_DESC_SETS = BIT(6),
TU_CMD_DIRTY_SHADER_CONSTS = BIT(7),
TU_CMD_DIRTY_LRZ = BIT(8),
TU_CMD_DIRTY_VS_PARAMS = BIT(9),
TU_CMD_DIRTY_PC_RASTER_CNTL = BIT(10),
TU_CMD_DIRTY_VIEWPORTS = BIT(11),
TU_CMD_DIRTY_SCISSORS = BIT(12),
TU_CMD_DIRTY_BLEND = BIT(13),
TU_CMD_DIRTY_PATCH_CONTROL_POINTS = BIT(14),
TU_CMD_DIRTY_DS = BIT(3),
TU_CMD_DIRTY_DESC_SETS = BIT(4),
TU_CMD_DIRTY_COMPUTE_DESC_SETS = BIT(5),
TU_CMD_DIRTY_SHADER_CONSTS = BIT(6),
TU_CMD_DIRTY_LRZ = BIT(7),
TU_CMD_DIRTY_VS_PARAMS = BIT(8),
TU_CMD_DIRTY_PC_RASTER_CNTL = BIT(9),
TU_CMD_DIRTY_VIEWPORTS = BIT(10),
TU_CMD_DIRTY_SCISSORS = BIT(11),
TU_CMD_DIRTY_BLEND = BIT(12),
TU_CMD_DIRTY_PATCH_CONTROL_POINTS = BIT(13),
/* all draw states were disabled and need to be re-enabled: */
TU_CMD_DIRTY_DRAW_STATE = BIT(15)
TU_CMD_DIRTY_DRAW_STATE = BIT(14)
};
/* There are only three cache domains we have to care about: the CCU, or

27
src/freedreno/vulkan/tu_pipeline.cc
View File

@@ -3663,26 +3663,26 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE:
pipeline->ds.rb_depth_cntl_mask &=
~(A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_DS);
break;
case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE:
pipeline->ds.rb_depth_cntl_mask &= ~A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_DS);
break;
case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP:
pipeline->ds.rb_depth_cntl_mask &= ~A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_DS);
break;
case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE:
pipeline->ds.rb_depth_cntl_mask &=
~(A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_DS);
break;
case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE:
pipeline->ds.rb_stencil_cntl_mask &= ~(A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
A6XX_RB_STENCIL_CONTROL_STENCIL_READ);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_STENCIL_CNTL);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_DS);
break;
case VK_DYNAMIC_STATE_STENCIL_OP:
pipeline->ds.rb_stencil_cntl_mask &= ~(A6XX_RB_STENCIL_CONTROL_FUNC__MASK |
@@ -3693,7 +3693,7 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK |
A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK |
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_STENCIL_CNTL);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_DS);
break;
case VK_DYNAMIC_STATE_DEPTH_BIAS_ENABLE:
pipeline->rast.gras_su_cntl_mask &= ~A6XX_GRAS_SU_CNTL_POLY_OFFSET;
@@ -3759,7 +3759,7 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
case VK_DYNAMIC_STATE_DEPTH_CLAMP_ENABLE_EXT:
pipeline->dynamic_state_mask |=
BIT(TU_DYNAMIC_STATE_RAST) |
BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
BIT(TU_DYNAMIC_STATE_DS);
pipeline->rast.gras_cl_cntl_mask &=
~A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE;
pipeline->rast.rb_depth_cntl_mask &=
@@ -3919,8 +3919,7 @@ tu_pipeline_builder_parse_libraries(struct tu_pipeline_builder *builder,
BIT(VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK) |
BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK) |
BIT(VK_DYNAMIC_STATE_STENCIL_REFERENCE) |
BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL) |
BIT(TU_DYNAMIC_STATE_RB_STENCIL_CNTL) |
BIT(TU_DYNAMIC_STATE_DS) |
BIT(VK_DYNAMIC_STATE_DEPTH_BOUNDS);
pipeline->shared_consts = library->shared_consts;
}
@@ -4437,11 +4436,6 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
}
pipeline->ds.rb_depth_cntl = rb_depth_cntl;
if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2)) {
tu_cs_emit_pkt4(&cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
tu_cs_emit(&cs, rb_stencil_cntl);
}
pipeline->ds.rb_stencil_cntl = rb_stencil_cntl;
/* the remaining draw states arent used if there is no d/s, leave them empty */
@@ -4495,7 +4489,10 @@ tu_pipeline_builder_parse_rast_ds(struct tu_pipeline_builder *builder,
pipeline->rast.rb_depth_cntl_mask & pipeline->ds.rb_depth_cntl_mask;
struct tu_cs cs;
if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2)) {
if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_DS, 4)) {
tu_cs_emit_pkt4(&cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
tu_cs_emit(&cs, pipeline->ds.rb_stencil_cntl);
tu_cs_emit_pkt4(&cs, REG_A6XX_RB_DEPTH_CNTL, 1);
if (pipeline->output.rb_depth_cntl_disable)
tu_cs_emit(&cs, 0);

3
src/freedreno/vulkan/tu_pipeline.h
View File

@@ -22,8 +22,7 @@ enum tu_dynamic_state
/* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
TU_DYNAMIC_STATE_SAMPLE_LOCATIONS_ENABLE,
TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
TU_DYNAMIC_STATE_RB_STENCIL_CNTL,
TU_DYNAMIC_STATE_DS,
TU_DYNAMIC_STATE_VB_STRIDE,
TU_DYNAMIC_STATE_PC_RASTER_CNTL,
TU_DYNAMIC_STATE_BLEND,