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ac/llvm,radv,radeonsi: pass instruction to intrinsic_load abi

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For simple intrinsic which also need other fields to translate
to LLVM like stream_id.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20158>
This commit is contained in:
Qiang Yu
2022-12-09 10:32:48 +08:00
parent 796a150196
commit 0ea589ec69
4 changed files with 7 additions and 7 deletions
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2
src/amd/llvm/ac_nir_to_llvm.c
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@@ -3619,7 +3619,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_load_ring_gsvs_amd: case nir_intrinsic_load_ring_gsvs_amd:
case nir_intrinsic_load_lds_ngg_scratch_base_amd: case nir_intrinsic_load_lds_ngg_scratch_base_amd:
case nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd: case nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd:
result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic); result = ctx->abi->intrinsic_load(ctx->abi, instr);
break; break;
case nir_intrinsic_load_merged_wave_info_amd: case nir_intrinsic_load_merged_wave_info_amd:
result = ac_get_arg(&ctx->ac, ctx->args->merged_wave_info); result = ac_get_arg(&ctx->ac, ctx->args->merged_wave_info);

2
src/amd/llvm/ac_shader_abi.h
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@@ -109,7 +109,7 @@ struct ac_shader_abi {
LLVMValueRef (*emit_fbfetch)(struct ac_shader_abi *abi); LLVMValueRef (*emit_fbfetch)(struct ac_shader_abi *abi);
LLVMValueRef (*intrinsic_load)(struct ac_shader_abi *abi, nir_intrinsic_op op); LLVMValueRef (*intrinsic_load)(struct ac_shader_abi *abi, nir_intrinsic_instr *intrin);
/* Whether to clamp the shadow reference value to [0,1]on GFX8. Radeonsi currently /* Whether to clamp the shadow reference value to [0,1]on GFX8. Radeonsi currently
* uses it due to promoting D16 to D32, but radv needs it off. */ * uses it due to promoting D16 to D32, but radv needs it off. */

6
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -1206,14 +1206,14 @@ declare_esgs_ring(struct radv_shader_context *ctx)
LLVMSetAlignment(ctx->esgs_ring, 64 * 1024); LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
} }
static LLVMValueRef radv_intrinsic_load(struct ac_shader_abi *abi, nir_intrinsic_op op) static LLVMValueRef radv_intrinsic_load(struct ac_shader_abi *abi, nir_intrinsic_instr *intrin)
{ {
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi); struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
switch (op) { switch (intrin->intrinsic) {
case nir_intrinsic_load_base_vertex: case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_first_vertex:
return radv_load_base_vertex(abi, op == nir_intrinsic_load_base_vertex); return radv_load_base_vertex(abi, intrin->intrinsic == nir_intrinsic_load_base_vertex);
case nir_intrinsic_load_ring_tess_factors_amd: case nir_intrinsic_load_ring_tess_factors_amd:
return ctx->hs_ring_tess_factor; return ctx->hs_ring_tess_factor;
case nir_intrinsic_load_ring_tess_offchip_amd: case nir_intrinsic_load_ring_tess_offchip_amd:

4
src/gallium/drivers/radeonsi/si_shader_llvm.c
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@@ -699,11 +699,11 @@ void si_build_wrapper_function(struct si_shader_context *ctx, struct ac_llvm_poi
LLVMBuildRet(builder, ret); LLVMBuildRet(builder, ret);
} }
static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op) static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_instr *intrin)
{ {
struct si_shader_context *ctx = si_shader_context_from_abi(abi); struct si_shader_context *ctx = si_shader_context_from_abi(abi);
switch (op) { switch (intrin->intrinsic) {
case nir_intrinsic_load_ring_tess_offchip_amd: case nir_intrinsic_load_ring_tess_offchip_amd:
return ctx->tess_offchip_ring; return ctx->tess_offchip_ring;