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r300: fix writemask for nir_intrinsic_load_ubo_vec4

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load_ubo_vec4 has always 4 components, however when translating to TGSI
just set the writemask according to the channels that are actually used
later. This is now done by deadcode analysis, but that one is going away
soon.

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26848>
This commit is contained in:
Pavel Ondračka
2023-12-21 11:43:50 +01:00
committed by Marge Bot
parent 43bdfebbff
commit 0e2e4688af
1 changed files with 7 additions and 1 deletions
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8
src/gallium/drivers/r300/compiler/nir_to_rc.c
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@@ -1048,7 +1048,13 @@ ntr_swizzle_for_write_mask(struct ureg_src src, uint32_t write_mask)
static struct ureg_dst
ntr_get_ssa_def_decl(struct ntr_compile *c, nir_def *ssa)
{
uint32_t writemask = BITSET_MASK(ssa->num_components);
uint32_t writemask;
/* Fix writemask for nir_intrinsic_load_ubo_vec4 accoring to uses. */
if (ssa->parent_instr->type == nir_instr_type_intrinsic &&
nir_instr_as_intrinsic(ssa->parent_instr)->intrinsic == nir_intrinsic_load_ubo_vec4)
writemask = nir_def_components_read(ssa);
else
writemask = BITSET_MASK(ssa->num_components);
struct ureg_dst dst;
if (!ntr_try_store_ssa_in_tgsi_output(c, &dst, ssa))