diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 282acd52003..7553f8d7d05 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1899,14 +1899,10 @@ gfx9_get_gs_info(const struct radv_pipeline_key *key, const struct radv_pipeline
 {
    const struct radv_physical_device *pdevice = pipeline->device->physical_device;
    struct radv_shader_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info;
-   struct radv_es_output_info *es_info;
+   struct radv_shader_info *es_info;
    bool has_tess = !!stages[MESA_SHADER_TESS_CTRL].nir;
 
-   if (pdevice->rad_info.gfx_level >= GFX9)
-      es_info = has_tess ? &gs_info->tes.es_info : &gs_info->vs.es_info;
-   else
-      es_info = has_tess ? &stages[MESA_SHADER_TESS_EVAL].info.tes.es_info
-                         : &stages[MESA_SHADER_VERTEX].info.vs.es_info;
+   es_info = has_tess ? &stages[MESA_SHADER_TESS_EVAL].info : &stages[MESA_SHADER_VERTEX].info;
 
    unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
    bool uses_adjacency;
@@ -2116,8 +2112,9 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi
 {
    const struct radv_physical_device *pdevice = pipeline->device->physical_device;
    struct radv_shader_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info;
-   struct radv_es_output_info *es_info =
-      stages[MESA_SHADER_TESS_CTRL].nir ? &gs_info->tes.es_info : &gs_info->vs.es_info;
+   struct radv_shader_info *es_info =
+      stages[MESA_SHADER_TESS_CTRL].nir ? &stages[MESA_SHADER_TESS_EVAL].info
+                                        : &stages[MESA_SHADER_VERTEX].info;
    unsigned gs_type = stages[MESA_SHADER_GEOMETRY].nir ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
    unsigned max_verts_per_prim = radv_get_num_input_vertices(stages);
    unsigned min_verts_per_prim = gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 66f66e5e621..81708b4615a 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -215,10 +215,6 @@ struct radv_vs_output_info {
    unsigned pos_exports;
 };
 
-struct radv_es_output_info {
-   uint32_t esgs_itemsize;
-};
-
 struct gfx9_gs_info {
    uint32_t vgt_gs_onchip_cntl;
    uint32_t vgt_gs_max_prims_per_subgroup;
@@ -256,6 +252,7 @@ struct radv_shader_info {
    bool has_ngg_early_prim_export;
    uint32_t num_lds_blocks_when_not_culling;
    uint32_t num_tess_patches;
+   uint32_t esgs_itemsize; /* Only for VS or TES as ES */
    unsigned workgroup_size;
    bool force_vrs_per_vertex;
    struct {
@@ -264,7 +261,6 @@ struct radv_shader_info {
       bool needs_draw_id;
       bool needs_instance_id;
       struct radv_vs_output_info outinfo;
-      struct radv_es_output_info es_info;
       bool as_es;
       bool as_ls;
       bool tcs_in_out_eq;
@@ -293,7 +289,6 @@ struct radv_shader_info {
    struct {
       uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
       struct radv_vs_output_info outinfo;
-      struct radv_es_output_info es_info;
       bool as_es;
       enum tess_primitive_mode _primitive_mode;
       enum gl_tess_spacing spacing;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index bd0de7353e3..3725f7623fa 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -696,12 +696,10 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
    /* Compute the ESGS item size for VS or TES as ES. */
    if ((nir->info.stage == MESA_SHADER_VERTEX && info->vs.as_es) ||
        (nir->info.stage == MESA_SHADER_TESS_EVAL && info->tes.as_es)) {
-      struct radv_es_output_info *es_info =
-         nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
       uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
                                         ? info->vs.num_linked_outputs
                                         : info->tes.num_linked_outputs;
-      es_info->esgs_itemsize = num_outputs_written * 16;
+      info->esgs_itemsize = num_outputs_written * 16;
    }
 
    if (nir->info.stage == MESA_SHADER_FRAGMENT) {