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intel/isl: add ISL_SURF_USAGE_SPARSE_BIT

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Vulkan Sparse resources have their own set of rules, so here we try to
make ISL aware of them through ISL_SURF_USAGE_SPARSE_BIT.

The big deal here is when some image ends up not using Tile64 nor
TileYs. Previously Ys was not supported on TGL at all, and Tile64 did
not have support for 3D. Now we still have some formats that end up
not being used with either Tile64 and Ys, but need to support Sparse
on them (e.g., YUV on Tile64). In the future we may have new tiling
formats or hardware restrictions that would force this case to happen
again.

So here we do some adjustments so we can make sparse work with other
tiling formats, although with limited functionality (e.g., those
formats may be restricted to opaque binds, and certainly don't support
the standard block shapes).

v2: before we had Ys support, we had defined TGL's block size as 4k.
v3: move the size_B chunk to before nte notify_failure() checks (Ken).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
This commit is contained in:
Paulo Zanoni
2023-04-21 16:33:00 -07:00
committed by Marge Bot
parent 968cefbff1
commit 0de5d142e8
2 changed files with 26 additions and 0 deletions
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25
src/intel/isl/isl.c
View File

@@ -1003,6 +1003,15 @@ isl_surf_choose_tiling(const struct isl_device *dev,
CHOOSE(ISL_TILING_LINEAR);
}
/* For sparse images, prefer the formats that use the standard block
* shapes.
*/
if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) {
CHOOSE(ISL_TILING_64);
CHOOSE(ISL_TILING_ICL_Ys);
CHOOSE(ISL_TILING_SKL_Ys);
}
/* Choose suggested 4K tilings first, then 64K tilings:
*
* Then following quotes can be found in the SKL PRMs,
@@ -2454,6 +2463,14 @@ isl_calc_size(const struct isl_device *dev,
row_pitch_B;
}
/* If for some reason we can't support the appropriate tiling format and
* end up falling to linear or some other format, make sure the image size
* and alignment are aligned to the expected block size so we can at least
* do opaque binds.
*/
if (info->usage & ISL_SURF_USAGE_SPARSE_BIT)
size_B = isl_align(size_B, 64 * 1024);
if (ISL_GFX_VER(dev) < 9) {
/* From the Broadwell PRM Vol 5, Surface Layout:
*
@@ -2563,6 +2580,14 @@ isl_calc_base_alignment(const struct isl_device *dev,
}
}
/* If for some reason we can't support the appropriate tiling format and
* end up falling to linear or some other format, make sure the image size
* and alignment are aligned to the expected block size so we can at least
* do opaque binds.
*/
if (info->usage & ISL_SURF_USAGE_SPARSE_BIT)
base_alignment_B = MAX(base_alignment_B, 64 * 1024);
return base_alignment_B;
}

1
src/intel/isl/isl.h
View File

@@ -1128,6 +1128,7 @@ typedef uint64_t isl_surf_usage_flags_t;
#define ISL_SURF_USAGE_VIDEO_DECODE_BIT (1u << 17)
#define ISL_SURF_USAGE_STREAM_OUT_BIT (1u << 18)
#define ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT (1u << 19)
#define ISL_SURF_USAGE_SPARSE_BIT (1u << 20)
/** @} */
/**