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i965/blorp: Loosen assertions in compute_msaa_layout_for_pipeline.

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Previously, on Gen7, compute_msaa_layout_for_pipeline() would verify
that IMS layout is not used.  However, now that we configure
SURFACE_STATE correctly for IMS surfaces, IMS layout is available.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Paul Berry
2012-07-09 12:50:31 -07:00
parent 989218b980
commit 0dd5e98aa5
1 changed files with 2 additions and 7 deletions
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9
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
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@@ -1432,20 +1432,15 @@ compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples,
assert(true_layout == INTEL_MSAA_LAYOUT_NONE ||
true_layout == INTEL_MSAA_LAYOUT_IMS);
return INTEL_MSAA_LAYOUT_NONE;
} else {
assert(true_layout != INTEL_MSAA_LAYOUT_NONE);
}
/* Prior to Gen7, all MSAA surfaces use IMS layout. */
if (brw->intel.gen == 6) {
assert(true_layout == INTEL_MSAA_LAYOUT_IMS);
return INTEL_MSAA_LAYOUT_IMS;
}
/* Since blorp uses color textures and render targets to do all its work
* (even when blitting stencil and depth data), we always have to configure
* the Gen7 GPU to use UMS or CMS layout on Gen7.
*/
assert(true_layout == INTEL_MSAA_LAYOUT_UMS ||
true_layout == INTEL_MSAA_LAYOUT_CMS);
return true_layout;
}