From 0dc2a5bfee682f3ed5610e3deee568a8f16b9930 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 29 Aug 2024 10:18:15 +0200 Subject: [PATCH] radv: pass the vertex shader to radv_write_vertex_descriptors() Mostly for DGC. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 12 ++++++------ src/amd/vulkan/radv_cmd_buffer.h | 3 ++- src/amd/vulkan/radv_device_generated_commands.c | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 592ff5cf3ae..df53c194d32 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6145,17 +6145,17 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag } void -radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, bool full_null_descriptors, void *vb_ptr) +radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *vs, + bool full_null_descriptors, void *vb_ptr) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radv_shader *vs_shader = radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_VERTEX); enum amd_gfx_level chip = pdev->info.gfx_level; enum radeon_family family = pdev->info.family; unsigned desc_index = 0; - uint32_t mask = vs_shader->info.vs.vb_desc_usage_mask; + uint32_t mask = vs->info.vs.vb_desc_usage_mask; uint64_t va; - const bool uses_dynamic_inputs = vs_shader->info.vs.dynamic_inputs; + const bool uses_dynamic_inputs = vs->info.vs.dynamic_inputs; const struct radv_vertex_input_state *vi_state = &cmd_buffer->state.vertex_input; const struct ac_vtx_format_info *vtx_info_table = @@ -6236,7 +6236,7 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, bool ful num_records = vk_buffer_range(&buffer->vk, offset, VK_WHOLE_SIZE); } - if (vs_shader->info.vs.use_per_attribute_vb_descs) { + if (vs->info.vs.use_per_attribute_vb_descs) { const uint32_t attrib_end = vi_state->offsets[i] + vi_state->format_sizes[i]; if (num_records < attrib_end) { @@ -6322,7 +6322,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) if (!radv_cmd_buffer_upload_alloc(cmd_buffer, vb_desc_alloc_size, &vb_offset, &vb_ptr)) return; - radv_write_vertex_descriptors(cmd_buffer, false, vb_ptr); + radv_write_vertex_descriptors(cmd_buffer, vs, false, vb_ptr); va = radv_buffer_get_va(cmd_buffer->upload.upload_bo); va += vb_offset; diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 5160f8ecd49..741ec8068b5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -704,7 +704,8 @@ void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const unsigned radv_instance_rate_prolog_index(unsigned num_attributes, uint32_t instance_rate_inputs); -void radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, bool full_null_descriptors, void *vb_ptr); +void radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *vs, + bool full_null_descriptors, void *vb_ptr); enum radv_cmd_flush_bits radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_stages, VkAccessFlags2 src_flags, const struct radv_image *image); diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index a1663003c60..7bfc59e1fc6 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -2343,7 +2343,7 @@ radv_prepare_dgc_graphics(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedC uint32_t mask = vs->info.vs.vb_desc_usage_mask; unsigned vb_desc_alloc_size = util_bitcount(mask) * 16; - radv_write_vertex_descriptors(cmd_buffer, true, *upload_data); + radv_write_vertex_descriptors(cmd_buffer, vs, true, *upload_data); uint32_t *vbo_info = (uint32_t *)((char *)*upload_data + vb_desc_alloc_size);