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intel/fs/gen6: Constrain barycentric source of LINTERP during bank conflict mitigation.

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This avoids regressions on SNB due to the bank conflict mitigation
pass moving a VGRF-allocated barycentric vector to a misaligned
location, which would prevent the PLN instruction from being used.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez
2019-12-30 16:34:22 -08:00
parent 369aef851d
commit 0db4455c1f
1 changed files with 8 additions and 0 deletions
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8
src/intel/compiler/brw_fs_bank_conflicts.cpp
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@@ -567,6 +567,14 @@ namespace {
constrained[p.atom_of_reg(reg_of(inst->src[i]))] = true; constrained[p.atom_of_reg(reg_of(inst->src[i]))] = true;
} }
/* Preserve the original allocation of VGRFs used by the barycentric
* source of the LINTERP instruction on Gen6, since pair-aligned
* barycentrics allow the PLN instruction to be used.
*/
if (v->devinfo->has_pln && v->devinfo->gen <= 6 &&
inst->opcode == FS_OPCODE_LINTERP)
constrained[p.atom_of_reg(reg_of(inst->src[0]))] = true;
/* The location of the Gen7 MRF hack registers is hard-coded in the /* The location of the Gen7 MRF hack registers is hard-coded in the
* rest of the compiler back-end. Don't attempt to move them around. * rest of the compiler back-end. Don't attempt to move them around.
*/ */