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i965: Add perf debug for depth/stencil alignment workaround.

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Fixing these rendering bugs has been implicated in performance
regressions (which may be unfixable), but at least knowing that it's
happening should help diagnose those regressions.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Eric Anholt
2012-12-18 13:45:14 -08:00
parent e454b2d480
commit 0d6a722ec4
1 changed files with 16 additions and 0 deletions
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16
src/mesa/drivers/dri/i965/brw_misc_state.c
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@@ -370,6 +370,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
}
if (rebase_depth) {
perf_debug("HW workaround: blitting depth level %d to a temporary "
"to fix alignment (depth tile offset %d,%d)\n",
depth_irb->mt_level, tile_x, tile_y);
intel_renderbuffer_move_to_temp(intel, depth_irb);
/* In the case of stencil_irb being the same packed depth/stencil
* texture but not the same rb, make it point at our rebased mt, too.
@@ -427,6 +431,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
}
if (rebase_stencil) {
perf_debug("HW workaround: blitting stencil level %d to a temporary "
"to fix alignment (stencil tile offset %d,%d)\n",
stencil_irb->mt_level, stencil_tile_x, stencil_tile_y);
intel_renderbuffer_move_to_temp(intel, stencil_irb);
stencil_mt = get_stencil_miptree(stencil_irb);
@@ -443,6 +451,14 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw)
} else if (depth_irb && !rebase_depth) {
if (tile_x != stencil_tile_x ||
tile_y != stencil_tile_y) {
perf_debug("HW workaround: blitting depth level %d to a temporary "
"to match stencil level %d alignment (depth tile offset "
"%d,%d, stencil offset %d,%d)\n",
depth_irb->mt_level,
stencil_irb->mt_level,
tile_x, tile_y,
stencil_tile_x, stencil_tile_y);
intel_renderbuffer_move_to_temp(intel, depth_irb);
tile_x = depth_irb->draw_x & tile_mask_x;