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intel/isl/icl: Use halign 8 instead of 4 hw workaround

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v1 by Topi Pohjolainen
v2,v3 by Anuj Phogat:
- Apply for gen >= 11
- Remove wa_bug_xxx function
- Use helper functions

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Anuj Phogat
2018-10-29 14:38:58 +02:00
committed by Anuj Phogat
parent d861401554
commit 0d60621101
1 changed files with 21 additions and 8 deletions
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29
src/intel/isl/isl_gen8.c
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@@ -151,7 +151,13 @@ isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
*/ */
const uint32_t valign = 4; const uint32_t valign = 4;
bool needs_halign16 = false; /* XXX(chadv): I believe the hardware requires each image to be
* cache-aligned. If that's true, then defaulting to halign=4 is wrong for
* many formats. Depending on the format's block size, we may need to
* increase halign to 8.
*/
uint32_t halign = 4;
if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
/* From the Broadwell PRM, Volume 2d "Command Reference: Structures", /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
@@ -163,15 +169,22 @@ isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
* or CCS_E. Depth buffers, including those that own an auxiliary HiZ * or CCS_E. Depth buffers, including those that own an auxiliary HiZ
* surface, are handled above and do not require HALIGN_16. * surface, are handled above and do not require HALIGN_16.
*/ */
needs_halign16 = true; assert(halign <= 16);
halign = 16;
} }
/* XXX(chadv): I believe the hardware requires each image to be if (ISL_DEV_GEN(dev) >= 11 && isl_tiling_is_any_y(tiling) &&
* cache-aligned. If that's true, then defaulting to halign=4 is wrong for fmtl->bpb == 32 && info->samples == 1) {
* many formats. Depending on the format's block size, we may need to /* GEN_BUG_1406667188: Pixel Corruption in subspan combining (8x4
* increase halign to 8. * combining) scenarios if halign=4.
*/ *
const uint32_t halign = needs_halign16 ? 16 : 4; * See RENDER_SURFACE_STATE in Ice Lake h/w spec:
*
* "For surface format = 32 bpp, num_multisamples = 1 , MIpcount > 0
* and surface walk = TiledY, HALIGN must be programmed to 8"
*/
halign = MAX(halign, 8);
}
*image_align_el = isl_extent3d(halign, valign, 1); *image_align_el = isl_extent3d(halign, valign, 1);
} }