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intel/fs: Add an alignment to VARYING_PULL_CONSTANT_LOAD_LOGICAL

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3932>
This commit is contained in:
Jason Ekstrand
2020-02-21 10:59:38 -06:00
parent 459f68af3c
commit 0d462dbee5
3 changed files with 9 additions and 5 deletions
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8
src/intel/compiler/brw_fs.cpp
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@@ -166,7 +166,8 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
const fs_reg &dst, const fs_reg &dst,
const fs_reg &surf_index, const fs_reg &surf_index,
const fs_reg &varying_offset, const fs_reg &varying_offset,
uint32_t const_offset) uint32_t const_offset,
uint8_t alignment)
{ {
/* We have our constant surface use a pitch of 4 bytes, so our index can /* We have our constant surface use a pitch of 4 bytes, so our index can
* be any component of a vector, and then we load 4 contiguous * be any component of a vector, and then we load 4 contiguous
@@ -190,7 +191,8 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
*/ */
fs_reg vec4_result = bld.vgrf(BRW_REGISTER_TYPE_F, 4); fs_reg vec4_result = bld.vgrf(BRW_REGISTER_TYPE_F, 4);
fs_inst *inst = bld.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, fs_inst *inst = bld.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
vec4_result, surf_index, vec4_offset); vec4_result, surf_index, vec4_offset,
brw_imm_ud(alignment));
inst->size_written = 4 * vec4_result.component_size(inst->exec_size); inst->size_written = 4 * vec4_result.component_size(inst->exec_size);
shuffle_from_32bit_read(bld, dst, vec4_result, shuffle_from_32bit_read(bld, dst, vec4_result,
@@ -2602,7 +2604,7 @@ fs_visitor::lower_constant_loads()
VARYING_PULL_CONSTANT_LOAD(ibld, inst->dst, VARYING_PULL_CONSTANT_LOAD(ibld, inst->dst,
brw_imm_ud(index), brw_imm_ud(index),
inst->src[1], inst->src[1],
pull_index * 4); pull_index * 4, 4);
inst->remove(block); inst->remove(block);
} }
} }

3
src/intel/compiler/brw_fs.h
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@@ -117,7 +117,8 @@ public:
const fs_reg &dst, const fs_reg &dst,
const fs_reg &surf_index, const fs_reg &surf_index,
const fs_reg &varying_offset, const fs_reg &varying_offset,
uint32_t const_offset); uint32_t const_offset,
uint8_t alignment);
void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf); void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
bool run_fs(bool allow_spilling, bool do_rep_send); bool run_fs(bool allow_spilling, bool do_rep_send);

3
src/intel/compiler/brw_fs_nir.cpp
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@@ -4501,7 +4501,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
for (int i = 0; i < instr->num_components; i++) for (int i = 0; i < instr->num_components; i++)
VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index, VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
base_offset, i * type_sz(dest.type)); base_offset, i * type_sz(dest.type),
nir_dest_bit_size(instr->dest) / 8);
prog_data->has_ubo_pull = true; prog_data->has_ubo_pull = true;
} else { } else {