From 0bd897989efea47474e73c8fa8ed64510bc403df Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 17 Jul 2024 13:50:35 -0400 Subject: [PATCH] asahi: drop unused patch index buffer lowering Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/lib/agx_nir_lower_gs.h | 3 +-- src/asahi/lib/agx_nir_lower_ia.c | 24 +++++++----------------- src/asahi/lib/agx_nir_prolog_epilog.c | 2 +- 3 files changed, 9 insertions(+), 20 deletions(-) diff --git a/src/asahi/lib/agx_nir_lower_gs.h b/src/asahi/lib/agx_nir_lower_gs.h index 953fd5ac9eb..0a970d8c70b 100644 --- a/src/asahi/lib/agx_nir_lower_gs.h +++ b/src/asahi/lib/agx_nir_lower_gs.h @@ -24,8 +24,7 @@ struct nir_def *agx_load_per_vertex_input(struct nir_builder *b, nir_intrinsic_instr *intr, struct nir_def *vertex); -bool agx_nir_lower_index_buffer(struct nir_shader *s, unsigned index_size_B, - bool patches); +bool agx_nir_lower_index_buffer(struct nir_shader *s, unsigned index_size_B); bool agx_nir_lower_sw_vs_id(nir_shader *s); diff --git a/src/asahi/lib/agx_nir_lower_ia.c b/src/asahi/lib/agx_nir_lower_ia.c index d2e79474997..89893fc014c 100644 --- a/src/asahi/lib/agx_nir_lower_ia.c +++ b/src/asahi/lib/agx_nir_lower_ia.c @@ -19,29 +19,19 @@ * vertex shaders, as part of geometry/tessellation lowering. It does not apply * the topology, which happens in the geometry shader. */ -struct state { - unsigned index_size; - bool patches; -}; - static nir_def * -load_vertex_id(nir_builder *b, struct state *state) +load_vertex_id(nir_builder *b, unsigned index_size_B) { nir_def *id = nir_load_primitive_id(b); - if (state->patches) { - id = nir_iadd(b, nir_imul(b, id, nir_load_patch_vertices_in(b)), - nir_load_invocation_id(b)); - } - /* If drawing with an index buffer, pull the vertex ID. Otherwise, the * vertex ID is just the index as-is. */ - if (state->index_size) { + if (index_size_B) { nir_def *ia = nir_load_input_assembly_buffer_agx(b); nir_def *index = - libagx_load_index_buffer(b, ia, id, nir_imm_int(b, state->index_size)); + libagx_load_index_buffer(b, ia, id, nir_imm_int(b, index_size_B)); id = nir_u2uN(b, index, id->bit_size); } @@ -58,16 +48,16 @@ lower_vertex_id(nir_builder *b, nir_intrinsic_instr *intr, void *data) if (intr->intrinsic != nir_intrinsic_load_vertex_id) return false; + unsigned *index_size_B = data; b->cursor = nir_instr_remove(&intr->instr); assert(intr->def.bit_size == 32); - nir_def_rewrite_uses(&intr->def, load_vertex_id(b, data)); + nir_def_rewrite_uses(&intr->def, load_vertex_id(b, *index_size_B)); return true; } bool -agx_nir_lower_index_buffer(nir_shader *s, unsigned index_size_B, bool patches) +agx_nir_lower_index_buffer(nir_shader *s, unsigned index_size_B) { return nir_shader_intrinsics_pass(s, lower_vertex_id, - nir_metadata_control_flow, - &(struct state){index_size_B, patches}); + nir_metadata_control_flow, &index_size_B); } diff --git a/src/asahi/lib/agx_nir_prolog_epilog.c b/src/asahi/lib/agx_nir_prolog_epilog.c index 6f0746933f5..6dc74c6fc61 100644 --- a/src/asahi/lib/agx_nir_prolog_epilog.c +++ b/src/asahi/lib/agx_nir_prolog_epilog.c @@ -169,7 +169,7 @@ agx_nir_vs_prolog(nir_builder *b, const void *key_) lower_vbo(b->shader, key->attribs, key->robustness); if (!key->hw) { - agx_nir_lower_index_buffer(b->shader, key->sw_index_size_B, false); + agx_nir_lower_index_buffer(b->shader, key->sw_index_size_B); agx_nir_lower_sw_vs_id(b->shader); }