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isl: Change the physical size of a W-tile to 128x32

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Reviewed-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Jason Ekstrand
2016-07-08 17:24:19 -07:00
parent 4b62c19c32
commit 0bd3a7e931
4 changed files with 15 additions and 19 deletions
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14
src/intel/isl/isl.c
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@@ -133,10 +133,20 @@ isl_tiling_get_info(const struct isl_device *dev,
break;
case ISL_TILING_W:
/* XXX: Should W tile be same as Y? */
assert(bs == 1);
logical_el = isl_extent2d(64, 64);
phys_B = isl_extent2d(64, 64);
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
*
* "If the surface is a stencil buffer (and thus has Tile Mode set
* to TILEMODE_WMAJOR), the pitch must be set to 2x the value
* computed based on width, as the stencil buffer is stored with two
* rows interleaved."
*
* This, together with the fact that stencil buffers are referred to as
* being Y-tiled in the PRMs for older hardware implies that the
* physical size of a W-tile is actually the same as for a Y-tile.
*/
phys_B = isl_extent2d(128, 32);
break;
case ISL_TILING_Yf:

11
src/intel/isl/isl_surface_state.c
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@@ -298,16 +298,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
if (info->surf->tiling == ISL_TILING_W) {
/* From the Broadwell PRM documentation for this field:
*
* "If the surface is a stencil buffer (and thus has Tile Mode set
* to TILEMODE_WMAJOR), the pitch must be set to 2x the value
* computed based on width, as the stencil buffer is stored with
* two rows interleaved."
*/
s.SurfacePitch = info->surf->row_pitch * 2 - 1;
} else if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
/* For gen9 1-D textures, surface pitch is ignored */
s.SurfacePitch = 0;
} else {

2
src/intel/vulkan/anv_meta_blit2d.c
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@@ -540,7 +540,7 @@ anv_meta_blit2d_w_tiled_dst(struct anv_cmd_buffer *cmd_buffer,
.tiling = ISL_TILING_Y0,
.base_offset = dst->base_offset,
.bs = 1,
.pitch = dst->pitch * 2,
.pitch = dst->pitch,
};
struct blit2d_dst_temps dst_temps;

7
src/intel/vulkan/genX_cmd_buffer.c
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@@ -1112,12 +1112,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
#endif
sb.StencilBufferObjectControlState = GENX(MOCS),
/* Stencil buffers have strange pitch. The PRM says:
*
* The pitch must be set to 2x the value computed based on width,
* as the stencil buffer is stored with two rows interleaved.
*/
sb.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
sb.SurfacePitch = image->stencil_surface.isl.row_pitch - 1,
#if GEN_GEN >= 8
sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2,