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intel/compiler: Create and use struct for CS thread payload

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Move subgroup_id, that's only used by CS for verx10 < 125, as part of
the payload too -- even though is not, strictly speaking.

Note the thread execution of Task/Mesh is similar enough, so we make
their common struct inherit from cs_thread_payload.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
This commit is contained in:
Caio Oliveira
2022-08-22 21:47:02 -07:00
committed by Marge Bot
parent d8461e975a
commit 0b6e613de8
4 changed files with 50 additions and 22 deletions
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31
src/intel/compiler/brw_fs_thread_payload.cpp
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@@ -366,7 +366,37 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v,
runtime_check_aads_emit);
}
cs_thread_payload::cs_thread_payload(const fs_visitor &v)
{
/* See nir_setup_uniforms for subgroup_id in earlier versions. */
if (v.devinfo->verx10 >= 125)
subgroup_id_ = retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD);
/* TODO: Fill out uses_btd_stack_ids automatically */
num_regs = 1 + brw_cs_prog_data(v.prog_data)->uses_btd_stack_ids;
}
void
cs_thread_payload::load_subgroup_id(const fs_builder &bld,
fs_reg &dest) const
{
auto devinfo = bld.shader->devinfo;
dest = retype(dest, BRW_REGISTER_TYPE_UD);
if (subgroup_id_.file != BAD_FILE) {
assert(devinfo->verx10 >= 125);
bld.AND(dest, subgroup_id_, brw_imm_ud(INTEL_MASK(7, 0)));
} else {
assert(devinfo->verx10 < 125);
assert(gl_shader_stage_is_compute(bld.shader->stage));
int index = brw_get_subgroup_id_param_index(devinfo,
bld.shader->stage_prog_data);
bld.MOV(dest, fs_reg(UNIFORM, index, BRW_REGISTER_TYPE_UD));
}
}
task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
: cs_thread_payload(v)
{
/* Task and Mesh Shader Payloads (SIMD8 and SIMD16)
*
@@ -388,6 +418,7 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v)
*/
unsigned r = 0;
assert(subgroup_id_.file != BAD_FILE);
extended_parameter_0 = retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD);
urb_output = retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD);