intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size

[ Francisco Jerez: Simplify. ]

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

src/intel/compiler/brw_fs.cpp

@@ -6987,7 +6987,7 @@ fs_visitor::run_vs()
 {
    assert(stage == MESA_SHADER_VERTEX);
 
-   payload_ = new vs_thread_payload();
+   payload_ = new vs_thread_payload(*this);
 
    emit_nir_code();
 

src/intel/compiler/brw_fs.h

@@ -98,7 +98,7 @@ protected:
 };
 
 struct vs_thread_payload : public thread_payload {
-   vs_thread_payload();
+   vs_thread_payload(const fs_visitor &v);
 
    fs_reg urb_handles;
 };

src/intel/compiler/brw_fs_thread_payload.cpp

@@ -25,11 +25,18 @@
 
 using namespace brw;
 
-vs_thread_payload::vs_thread_payload()
+vs_thread_payload::vs_thread_payload(const fs_visitor &v)
 {
-   urb_handles = brw_ud8_grf(1, 0);
+   unsigned r = 0;
 
-   num_regs = 2;
+   /* R0: Thread header. */
+   r += reg_unit(v.devinfo);
+
+   /* R1: URB handles. */
+   urb_handles = brw_ud8_grf(r, 0);
+   r += reg_unit(v.devinfo);
+
+   num_regs = r;
 }
 
 tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)