gallium: Drop PIPE_SHADER_CAP_PREFERRED_IR.

Now everyone's saying NIR, and doing any NTT internally.  The only returns
of TGSI were in gallivm_get_shader_param() and
tgsi_exec_get_shader_param(), but the drivers were returning NIR instead
of calling down to them.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23114>

docs/gallium/screen.rst

@@ -741,8 +741,6 @@ support different features.
   Note that 16-bit constants are not lowered to uniforms in GLSL.
 * ``PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS``: The maximum number of texture
   samplers.
-* ``PIPE_SHADER_CAP_PREFERRED_IR``: Preferred representation of the
-  program.  It should be one of the ``pipe_shader_ir`` enum values.
 * ``PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS``: The maximum number of texture
   sampler views. Must not be lower than PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS.
 * ``PIPE_SHADER_CAP_DROUND_SUPPORTED``: Whether double precision rounding

src/gallium/auxiliary/draw/draw_vs.c

@@ -70,11 +70,8 @@ draw_create_vertex_shader(struct draw_context *draw,
    if (draw->pt.middle.llvm) {
       struct pipe_screen *screen = draw->pipe->screen;
       if (shader->type == PIPE_SHADER_IR_NIR &&
-          ((!screen->get_shader_param(screen, PIPE_SHADER_VERTEX,
+          !screen->get_shader_param(screen, PIPE_SHADER_VERTEX,
-                                     PIPE_SHADER_CAP_INTEGERS)) ||
+                                    PIPE_SHADER_CAP_INTEGERS)) {
-           (screen->get_shader_param(screen, PIPE_SHADER_VERTEX,
-                                     PIPE_SHADER_CAP_PREFERRED_IR) ==
-            PIPE_SHADER_IR_TGSI))) {
         state.type = PIPE_SHADER_IR_TGSI;
         state.tokens = nir_to_tgsi(shader->ir.nir, screen);
         is_allocated = true;

src/gallium/auxiliary/gallivm/lp_bld_limits.h

@@ -142,8 +142,6 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
       return PIPE_MAX_SAMPLERS;
    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
       return PIPE_MAX_SHADER_SAMPLER_VIEWS;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_TGSI;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:

src/gallium/auxiliary/tgsi/tgsi_exec.h

@@ -476,8 +476,6 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
       return PIPE_MAX_SAMPLERS;
    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
       return PIPE_MAX_SHADER_SAMPLER_VIEWS;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_TGSI;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return 1 << PIPE_SHADER_IR_TGSI;
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:

src/gallium/drivers/asahi/agx_pipe.c

@@ -1782,9 +1782,6 @@ agx_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
       return 16; /* XXX: How many? */
 
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
-
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return (1 << PIPE_SHADER_IR_NIR);
 

src/gallium/drivers/crocus/crocus_screen.c

@@ -521,8 +521,6 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return 1 << PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_DROUND_SUPPORTED:

src/gallium/drivers/d3d12/d3d12_screen.cpp

@@ -465,9 +465,6 @@ d3d12_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_FP16:
       return 0; /* not implemented */
 
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
-
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
       return 0; /* not implemented */
 

src/gallium/drivers/etnaviv/etnaviv_screen.c

@@ -410,8 +410,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
       return shader == PIPE_SHADER_FRAGMENT
                 ? screen->specs.fragment_sampler_count
                 : screen->specs.vertex_sampler_count;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
       if (ubo_enable)
          return 16384; /* 16384 so state tracker enables UBOs */

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -722,8 +722,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
       return 16;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return (1 << PIPE_SHADER_IR_NIR) |
              COND(has_compute(screen) && (shader == PIPE_SHADER_COMPUTE),

src/gallium/drivers/i915/i915_screen.c

@@ -281,8 +281,6 @@ i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
                       enum pipe_shader_cap cap)
 {
    switch (cap) {
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 

src/gallium/drivers/iris/iris_screen.c

@@ -544,8 +544,6 @@ iris_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
       return 0;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS: {
       int irs = 1 << PIPE_SHADER_IR_NIR;
       if (iris_enable_clover())

src/gallium/drivers/lima/lima_screen.c

@@ -229,9 +229,6 @@ get_vertex_shader_param(struct lima_screen *screen,
    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
       return 1;
 
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
-
    case PIPE_SHADER_CAP_MAX_TEMPS:
       return 256; /* need investigate */
 
@@ -271,9 +268,6 @@ get_fragment_shader_param(struct lima_screen *screen,
    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
       return 16; /* need investigate */
 
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
-
    case PIPE_SHADER_CAP_MAX_TEMPS:
       return 256; /* need investigate */
 

src/gallium/drivers/llvmpipe/lp_screen.c

@@ -385,8 +385,6 @@ llvmpipe_get_shader_param(struct pipe_screen *screen,
    case PIPE_SHADER_MESH:
    case PIPE_SHADER_TASK:
    case PIPE_SHADER_FRAGMENT:
-      if (param == PIPE_SHADER_CAP_PREFERRED_IR)
-         return PIPE_SHADER_IR_NIR;
       return gallivm_get_shader_param(param);
    case PIPE_SHADER_TESS_CTRL:
    case PIPE_SHADER_TESS_EVAL:
@@ -397,8 +395,6 @@ llvmpipe_get_shader_param(struct pipe_screen *screen,
    case PIPE_SHADER_VERTEX:
    case PIPE_SHADER_GEOMETRY:
       switch (param) {
-      case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
          /* At this time, the draw module and llvmpipe driver only
           * support vertex shader texture lookups when LLVM is enabled in

src/gallium/drivers/nouveau/nv30/nv30_screen.c

@@ -344,8 +344,6 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
          return 1;
       case PIPE_SHADER_CAP_MAX_TEMPS:
          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
-      case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
          return 0;
@@ -399,8 +397,6 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
          return 16;
-      case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
       case PIPE_SHADER_CAP_CONT_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:

src/gallium/drivers/nouveau/nv50/nv50_screen.c

@@ -373,8 +373,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
       return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
       return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return 1 << PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_DROUND_SUPPORTED:

src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

@@ -395,8 +395,6 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
    }
 
    switch (param) {
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS: {
       uint32_t irs = 1 << PIPE_SHADER_IR_NIR;
       if (screen->force_enable_cl)

src/gallium/drivers/panfrost/pan_screen.c

@@ -469,9 +469,6 @@ panfrost_get_shader_param(struct pipe_screen *screen,
       STATIC_ASSERT(PIPE_MAX_SHADER_SAMPLER_VIEWS < 0x10000);
       return PIPE_MAX_SHADER_SAMPLER_VIEWS;
 
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
-
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return (1 << PIPE_SHADER_IR_NIR);
 

src/gallium/drivers/r300/r300_screen.c

@@ -255,8 +255,6 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
    boolean is_r500 = r300screen->caps.is_r500;
 
    switch (param) {
-    case PIPE_SHADER_CAP_PREFERRED_IR:
-        return PIPE_SHADER_IR_NIR;
     case PIPE_SHADER_CAP_SUPPORTED_IRS:
         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
     default:

src/gallium/drivers/r600/r600_pipe.c

@@ -623,8 +623,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
 	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 		return 16;
-	case PIPE_SHADER_CAP_PREFERRED_IR:
-		return PIPE_SHADER_IR_NIR;
 	case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 		int ir = 0;
 		if (shader == PIPE_SHADER_COMPUTE)

src/gallium/drivers/radeonsi/si_get.c

@@ -463,8 +463,6 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
       return SI_NUM_SHADER_BUFFERS;
    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
       return SI_NUM_IMAGES;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
 
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       if (shader == PIPE_SHADER_COMPUTE) {

src/gallium/drivers/softpipe/sp_screen.c

@@ -326,8 +326,6 @@ softpipe_get_shader_param(struct pipe_screen *screen,
    struct softpipe_screen *sp_screen = softpipe_screen(screen);
 
    switch (param) {
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
    default:

src/gallium/drivers/svga/svga_screen.c

@@ -535,8 +535,6 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
          return 16;
-      case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
       case PIPE_SHADER_CAP_SUPPORTED_IRS:
          return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
       case PIPE_SHADER_CAP_DROUND_SUPPORTED:
@@ -599,8 +597,6 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
          return 0;
-      case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
       case PIPE_SHADER_CAP_SUPPORTED_IRS:
          return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
       case PIPE_SHADER_CAP_DROUND_SUPPORTED:
@@ -711,8 +707,6 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
       return sws->have_gl43 ? PIPE_MAX_SAMPLERS : SVGA3D_DX_MAX_SAMPLERS;
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
    case PIPE_SHADER_CAP_SUPPORTED_IRS:
       if (sws->have_gl43)
          return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);

src/gallium/drivers/v3d/v3d_screen.c

@@ -464,8 +464,6 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type s
                         return 0;
                 }
 
-        case PIPE_SHADER_CAP_PREFERRED_IR:
-                return PIPE_SHADER_IR_NIR;
         case PIPE_SHADER_CAP_SUPPORTED_IRS:
                 return 1 << PIPE_SHADER_IR_NIR;
         default:

src/gallium/drivers/vc4/vc4_screen.c

@@ -299,8 +299,6 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
                 return VC4_MAX_TEXTURE_SAMPLERS;
-        case PIPE_SHADER_CAP_PREFERRED_IR:
-                return PIPE_SHADER_IR_NIR;
         case PIPE_SHADER_CAP_SUPPORTED_IRS:
                 return 1 << PIPE_SHADER_IR_NIR;
         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:

src/gallium/drivers/virgl/virgl_screen.c

@@ -449,8 +449,6 @@ virgl_get_shader_param(struct pipe_screen *screen,
             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
          else
             return vscreen->caps.caps.v2.max_shader_image_other_stages;
-      case PIPE_SHADER_CAP_PREFERRED_IR:
-         return PIPE_SHADER_IR_NIR;
       case PIPE_SHADER_CAP_SUPPORTED_IRS:
          return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:

src/gallium/drivers/zink/zink_screen.c

@@ -1206,9 +1206,6 @@ zink_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_INT16:
       return screen->info.feats.features.shaderInt16;
 
-   case PIPE_SHADER_CAP_PREFERRED_IR:
-      return PIPE_SHADER_IR_NIR;
-
    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
       return 0; /* not implemented */
 

src/gallium/include/pipe/p_defines.h

@@ -1089,7 +1089,6 @@ enum pipe_shader_cap
    PIPE_SHADER_CAP_INT16,
    PIPE_SHADER_CAP_GLSL_16BIT_CONSTS,
    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
-   PIPE_SHADER_CAP_PREFERRED_IR,
    PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
    PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
    PIPE_SHADER_CAP_DROUND_SUPPORTED, /* all rounding modes */

src/gallium/include/pipe/p_state.h

@@ -282,12 +282,8 @@ struct pipe_stream_output_info
 };
 
 /**
- * The 'type' parameter identifies whether the shader state contains TGSI
+ * The 'type' parameter identifies whether the shader state contains NIR, TGSI
- * tokens, etc.  If the driver returns 'PIPE_SHADER_IR_TGSI' for the
+ * tokens, etc.
- * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be
- * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid.  If the driver
- * requests a different 'pipe_shader_ir' type, then it must check the 'type'
- * enum to see if it is getting TGSI tokens or its preferred IR.
  *
  * TODO pipe_compute_state should probably get similar treatment to handle
  * multiple IR's in a cleaner way..

src/mesa/state_tracker/st_cb_clear.c

@@ -108,10 +108,6 @@ st_destroy_clear(struct st_context *st)
 static void
 set_clearcolor_fs(struct st_context *st, union pipe_color_union *color)
 {
-   struct pipe_screen *pscreen = st->screen;
-   bool use_nir = PIPE_SHADER_IR_NIR ==
-      pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
-                                PIPE_SHADER_CAP_PREFERRED_IR);
    struct pipe_constant_buffer cb = {
       .user_buffer = color->f,
       .buffer_size = 4 * sizeof(float),
@@ -120,11 +116,7 @@ set_clearcolor_fs(struct st_context *st, union pipe_color_union *color)
                                 false, &cb);
 
    if (!st->clear.fs) {
-      if (use_nir) {
+      st->clear.fs = st_nir_make_clearcolor_shader(st);
-         st->clear.fs = st_nir_make_clearcolor_shader(st);
-      } else {
-         st->clear.fs = util_make_fs_clear_all_cbufs(st->pipe);
-      }
    }
 
    cso_set_fragment_shader_handle(st->cso_context, st->clear.fs);
@@ -155,29 +147,11 @@ make_nir_clear_vertex_shader(struct st_context *st, bool layered)
 static inline void
 set_vertex_shader(struct st_context *st)
 {
-   struct pipe_screen *pscreen = st->screen;
-   bool use_nir = PIPE_SHADER_IR_NIR ==
-      pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
-                                PIPE_SHADER_CAP_PREFERRED_IR);
-
    /* vertex shader - still required to provide the linkage between
     * fragment shader input semantics and vertex_element/buffers.
     */
    if (!st->clear.vs)
-   {
+      st->clear.vs = make_nir_clear_vertex_shader(st, false);
-      if (use_nir) {
-         st->clear.vs = make_nir_clear_vertex_shader(st, false);
-      } else {
-         const enum tgsi_semantic semantic_names[] = {
-            TGSI_SEMANTIC_POSITION,
-         };
-         const uint semantic_indexes[] = { 0 };
-         st->clear.vs = util_make_vertex_passthrough_shader(st->pipe, 1,
-                                                            semantic_names,
-                                                            semantic_indexes,
-                                                            FALSE);
-      }
-   }
 
    cso_set_vertex_shader_handle(st->cso_context, st->clear.vs);
    cso_set_geometry_shader_handle(st->cso_context, NULL);
@@ -188,10 +162,6 @@ static void
 set_vertex_shader_layered(struct st_context *st)
 {
    struct pipe_context *pipe = st->pipe;
-   struct pipe_screen *pscreen = st->screen;
-   bool use_nir = PIPE_SHADER_IR_NIR ==
-      pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
-                                PIPE_SHADER_CAP_PREFERRED_IR);
 
    if (!st->screen->get_param(st->screen, PIPE_CAP_VS_INSTANCEID)) {
       assert(!"Got layered clear, but VS instancing is unsupported");
@@ -203,9 +173,7 @@ set_vertex_shader_layered(struct st_context *st)
       bool vs_layer =
          st->screen->get_param(st->screen, PIPE_CAP_VS_LAYER_VIEWPORT);
       if (vs_layer) {
-         st->clear.vs_layered =
+         st->clear.vs_layered = make_nir_clear_vertex_shader(st, true);
-            use_nir ? make_nir_clear_vertex_shader(st, true)
-                    : util_make_layered_clear_vertex_shader(pipe);
       } else {
          st->clear.vs_layered = util_make_layered_clear_helper_vertex_shader(pipe);
          st->clear.gs_layered = util_make_layered_clear_geometry_shader(pipe);

src/mesa/state_tracker/st_cb_drawtex.c

@@ -95,8 +95,6 @@ lookup_shader(struct st_context *st,
               const enum tgsi_semantic *semantic_names,
               const uint *semantic_indexes)
 {
-   struct pipe_context *pipe = st->pipe;
-   struct pipe_screen *screen = st->screen;
    GLuint i, j;
 
    /* look for existing shader with same attributes */
@@ -126,32 +124,20 @@ lookup_shader(struct st_context *st,
       CachedShaders[i].semantic_indexes[j] = semantic_indexes[j];
    }
 
-   enum pipe_shader_ir preferred_ir =
+   unsigned inputs[2 + MAX_TEXTURE_UNITS];
-      screen->get_shader_param(screen, PIPE_SHADER_VERTEX,
+   unsigned outputs[2 + MAX_TEXTURE_UNITS];
-                               PIPE_SHADER_CAP_PREFERRED_IR);
 
-   if (preferred_ir == PIPE_SHADER_IR_NIR) {
+   for (int j = 0; j < num_attribs; j++) {
-      unsigned inputs[2 + MAX_TEXTURE_UNITS];
+      inputs[j] = semantic_to_vert_attrib(semantic_names[j]);
-      unsigned outputs[2 + MAX_TEXTURE_UNITS];
+      outputs[j] = semantic_to_varying_slot(semantic_names[j]);
-
-      for (int j = 0; j < num_attribs; j++) {
-         inputs[j] = semantic_to_vert_attrib(semantic_names[j]);
-         outputs[j] = semantic_to_varying_slot(semantic_names[j]);
-      }
-
-      CachedShaders[i].handle =
-         st_nir_make_passthrough_shader(st, "st/drawtex VS",
-                                        MESA_SHADER_VERTEX,
-                                        num_attribs, inputs,
-                                        outputs, NULL, 0);
-   } else {
-      CachedShaders[i].handle =
-         util_make_vertex_passthrough_shader(pipe,
-                                             num_attribs,
-                                             semantic_names,
-                                             semantic_indexes, FALSE);
    }
 
+   CachedShaders[i].handle =
+      st_nir_make_passthrough_shader(st, "st/drawtex VS",
+                                       MESA_SHADER_VERTEX,
+                                       num_attribs, inputs,
+                                       outputs, NULL, 0);
+
    NumCachedShaders++;
 
    return CachedShaders[i].handle;

src/mesa/state_tracker/st_extensions.c

@@ -175,8 +175,6 @@ void st_init_limits(struct pipe_screen *screen,
          &c->ShaderCompilerOptions[stage];
       struct gl_program_constants *pc = &c->Program[stage];
 
-      bool prefer_nir = PIPE_SHADER_IR_NIR ==
-         screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_PREFERRED_IR);
       if (screen->get_compiler_options)
          options->NirOptions = screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, sh);
 
@@ -363,21 +361,16 @@ void st_init_limits(struct pipe_screen *screen,
             options->LowerBuiltinVariablesXfb |= VARYING_BIT_PSIZ;
       }
 
-      /* Note: If the driver doesn't prefer NIR, then st_create_nir_shader()
+      options->LowerPrecisionFloat16 =
-       * will call nir_to_tgsi, and TGSI doesn't support 16-bit ops.
+         screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_FP16);
-       */
+      options->LowerPrecisionDerivatives =
-      if (prefer_nir) {
+         screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_FP16_DERIVATIVES);
-         options->LowerPrecisionFloat16 =
+      options->LowerPrecisionInt16 =
-            screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_FP16);
+         screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_INT16);
-         options->LowerPrecisionDerivatives =
+      options->LowerPrecisionConstants =
-            screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_FP16_DERIVATIVES);
+         screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_GLSL_16BIT_CONSTS);
-         options->LowerPrecisionInt16 =
+      options->LowerPrecisionFloat16Uniforms =
-            screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_INT16);
+         screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_FP16_CONST_BUFFERS);
-         options->LowerPrecisionConstants =
-            screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_GLSL_16BIT_CONSTS);
-         options->LowerPrecisionFloat16Uniforms =
-            screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_FP16_CONST_BUFFERS);
-      }
    }
 
    c->MaxUserAssignableUniformLocations =
@@ -1840,13 +1833,10 @@ void st_init_extensions(struct pipe_screen *screen,
       screen->get_param(screen, PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER);
    consts->GLThreadNopCheckFramebufferStatus = options->glthread_nop_check_framebuffer_status;
 
-   bool prefer_nir = PIPE_SHADER_IR_NIR ==
-         screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_PREFERRED_IR);
    const struct nir_shader_compiler_options *nir_options =
       consts->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].NirOptions;
 
-   if (prefer_nir &&
+   if (screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS) &&
-       screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS) &&
        extensions->ARB_stencil_texturing &&
        screen->get_param(screen, PIPE_CAP_DOUBLES) &&
        !(nir_options->lower_doubles_options & nir_lower_fp64_full_software))

src/mesa/state_tracker/st_program.c

@@ -49,11 +49,8 @@
 #include "pipe/p_defines.h"
 #include "pipe/p_shader_tokens.h"
 #include "draw/draw_context.h"
-#include "tgsi/tgsi_dump.h"
 #include "tgsi/tgsi_parse.h"
 #include "tgsi/tgsi_ureg.h"
-#include "nir_builder.h"
-#include "nir/nir_to_tgsi.h"
 
 #include "util/u_memory.h"
 
@@ -503,37 +500,17 @@ struct pipe_shader_state *
 st_create_nir_shader(struct st_context *st, struct pipe_shader_state *state)
 {
    struct pipe_context *pipe = st->pipe;
-   struct pipe_screen *screen = st->screen;
 
    assert(state->type == PIPE_SHADER_IR_NIR);
    nir_shader *nir = state->ir.nir;
    struct shader_info info = nir->info;
    gl_shader_stage stage = nir->info.stage;
-   enum pipe_shader_type sh = pipe_shader_type_from_mesa(stage);
 
    if (ST_DEBUG & DEBUG_PRINT_IR) {
       fprintf(stderr, "NIR before handing off to driver:\n");
       nir_print_shader(nir, stderr);
    }
 
-   if (PIPE_SHADER_IR_NIR !=
-       screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_PREFERRED_IR)) {
-      /* u_screen.c defaults to images as deref enabled for some reason (which
-       * is what radeonsi wants), but nir-to-tgsi requires lowered images.
-       */
-      if (screen->get_param(screen, PIPE_CAP_NIR_IMAGES_AS_DEREF))
-         NIR_PASS_V(nir, gl_nir_lower_images, false);
-
-      state->type = PIPE_SHADER_IR_TGSI;
-      state->tokens = nir_to_tgsi(nir, screen);
-
-      if (ST_DEBUG & DEBUG_PRINT_IR) {
-         fprintf(stderr, "TGSI for driver after nir-to-tgsi:\n");
-         tgsi_dump(state->tokens, 0);
-         fprintf(stderr, "\n");
-      }
-   }
-
    struct pipe_shader_state *shader;
    switch (stage) {
    case MESA_SHADER_VERTEX: