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Revert "radv: set BIG_PAGE to improve performance on GFX10.3"

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This reverts commit f4d861696d.

Turns out we cannot use BIG_PAGE with GTT and we can't tell
when a buffer is spilled to GTT.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6726>
This commit is contained in:
Bas Nieuwenhuizen
2020-09-15 12:54:03 +02:00
committed by Marge Bot
parent d78df70c2a
commit 0a84c595c2
2 changed files with 3 additions and 19 deletions
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18
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1750,9 +1750,6 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
}
bool zs_big_page = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
(image->alignment % (64 * 1024) == 0);
radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
@@ -1778,9 +1775,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
S_02807C_HTILE_RD_POLICY(meta_read_policy) |
S_02807C_Z_BIG_PAGE(zs_big_page) |
S_02807C_S_BIG_PAGE(zs_big_page));
S_02807C_HTILE_RD_POLICY(meta_read_policy));
} else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
@@ -2255,7 +2250,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
int i;
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
bool color_big_page = true;
/* this may happen for inherited secondary recording */
if (!framebuffer)
@@ -2280,12 +2274,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
radv_load_color_clear_metadata(cmd_buffer, iview, i);
/* BIG_PAGE is an optimization that can only be enabled if all
* color targets are compatible.
*/
color_big_page &= cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&
(iview->image->alignment % (64 * 1024) == 0);
}
if (subpass->depth_stencil_attachment) {
@@ -2348,9 +2336,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
S_028410_CMASK_RD_POLICY(meta_read_policy) |
S_028410_FMASK_RD_POLICY(meta_read_policy) |
S_028410_DCC_RD_POLICY(meta_read_policy) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
S_028410_FMASK_BIG_PAGE(color_big_page) |
S_028410_COLOR_BIG_PAGE(color_big_page));
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA));
}
if (cmd_buffer->device->dfsm_allowed) {

4
src/amd/vulkan/radv_image.c
View File

@@ -843,9 +843,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
S_00A014_MAX_MIP(image->info.samples > 1 ?
util_logbase2(image->info.samples) :
image->info.levels - 1) |
S_00A014_PERF_MOD(4) |
S_00A014_BIG_PAGE(device->physical_device->rad_info.chip_class >= GFX10_3 &&
image->alignment % (64 * 1024) == 0);
S_00A014_PERF_MOD(4);
state[6] = 0;
state[7] = 0;