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radv: invalidate L2 instead of only writeback L2 when using DCC stores

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It seems INV_L2 is the right thing to do, especially for RDNA2 chips
with non-coherent RBs (NAVI22 is one of these). This fixes DCC
corruption.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6476
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7507
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19516>
(cherry picked from commit 06adf6ad11)
This commit is contained in:
Samuel Pitoiset
2022-11-02 11:27:13 +01:00
committed by Dylan Baker
parent 9855c364a1
commit 0971b56a90
2 changed files with 2 additions and 5 deletions
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2
.pick_status.json
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@@ -859,7 +859,7 @@
"description": "radv: invalidate L2 instead of only writeback L2 when using DCC stores",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

5
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -4357,11 +4357,8 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 src_fla
}
}
/* This is valid even for the rb_noncoherent_dirty case, because with how we account for
* dirtyness, if it isn't dirty it doesn't contain the data at all and hence doesn't need
* invalidating. */
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_WB_L2;
flush_bits |= RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR:
case VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT: