From 08ca862ef842bcd63a23ae6edaf9c4184da3d632 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Wed, 12 Oct 2022 15:32:01 -0700 Subject: [PATCH] intel/compiler: Tighter src and dest size bounds checking for some opcodes Enforce the sizes listed in the Skylake PRM: BFREV: source types: *D destination types: *D CBIT: source types: UB, UW, UD destination types: UD FBH: source types: D, UD destination types: UD FBL: source types: UD destination types: UD LZD: source types: D, UD destination types: UD v2: Update BFREV commit message documentation. Suggested by Ken. Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 16 +++++++++++----- src/intel/compiler/brw_vec4_nir.cpp | 12 ++++++++---- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 0215dcde42f..ed803865627 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1666,28 +1666,33 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, break; case nir_op_bitfield_reverse: - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); bld.BFREV(result, op[0]); break; case nir_op_bit_count: - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) < 64); bld.CBIT(result, op[0]); break; case nir_op_ufind_msb: { - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); emit_find_msb_using_lzd(bld, result, op[0]); break; } case nir_op_uclz: assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); bld.LZD(retype(result, BRW_REGISTER_TYPE_UD), op[0]); break; case nir_op_ifind_msb: { - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]); @@ -1706,7 +1711,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, } case nir_op_find_lsb: - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); bld.FBL(result, op[0]); break; diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index a490f010f07..04bf09d2338 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1623,12 +1623,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_bitfield_reverse: - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); emit(BFREV(dst, op[0])); break; case nir_op_bit_count: - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) < 64); emit(CBIT(dst, op[0])); break; @@ -1638,7 +1640,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_ifind_msb: { - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); vec4_builder bld = vec4_builder(this).at_end(); @@ -1660,7 +1663,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } case nir_op_find_lsb: - assert(nir_dest_bit_size(instr->dest.dest) < 64); + assert(nir_dest_bit_size(instr->dest.dest) == 32); + assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); emit(FBL(dst, op[0])); break;