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radv: rename radv_pipeline_stage to radv_shader_stage

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It's more generic and it will fit shader object just well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24313>
This commit is contained in:
Samuel Pitoiset
2023-07-25 09:56:44 +02:00
committed by Marge Bot
parent 090d88247d
commit 08bfcc12d4
14 changed files with 91 additions and 92 deletions
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8
src/amd/vulkan/nir/radv_nir.h
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@@ -37,7 +37,7 @@ typedef struct nir_shader nir_shader;
struct radeon_info; struct radeon_info;
struct radv_pipeline_layout; struct radv_pipeline_layout;
struct radv_pipeline_key; struct radv_pipeline_key;
struct radv_pipeline_stage; struct radv_shader_stage;
struct radv_shader_info; struct radv_shader_info;
struct radv_shader_args; struct radv_shader_args;
struct radv_device; struct radv_device;
@@ -52,12 +52,12 @@ void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const
bool radv_nir_lower_ray_queries(struct nir_shader *shader, struct radv_device *device); bool radv_nir_lower_ray_queries(struct nir_shader *shader, struct radv_device *device);
bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_pipeline_stage *vs_stage, bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_shader_stage *vs_stage,
const struct radv_pipeline_key *pl_key, const struct radeon_info *rad_info); const struct radv_pipeline_key *pl_key, const struct radeon_info *rad_info);
bool radv_nir_lower_primitive_shading_rate(nir_shader *nir, enum amd_gfx_level gfx_level); bool radv_nir_lower_primitive_shading_rate(nir_shader *nir, enum amd_gfx_level gfx_level);
bool radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_stage, bool radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stage *fs_stage,
const struct radv_pipeline_key *key); const struct radv_pipeline_key *key);
bool radv_nir_lower_fs_barycentric(nir_shader *shader, const struct radv_pipeline_key *key, unsigned rast_prim); bool radv_nir_lower_fs_barycentric(nir_shader *shader, const struct radv_pipeline_key *key, unsigned rast_prim);
@@ -74,7 +74,7 @@ void radv_nir_lower_io_to_scalar_early(nir_shader *nir, nir_variable_mode mask);
void radv_nir_lower_io(struct radv_device *device, nir_shader *nir); void radv_nir_lower_io(struct radv_device *device, nir_shader *nir);
bool radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *stage); bool radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *stage);
void radv_nir_lower_poly_line_smooth(nir_shader *nir, const struct radv_pipeline_key *key); void radv_nir_lower_poly_line_smooth(nir_shader *nir, const struct radv_pipeline_key *key);

2
src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c
View File

@@ -29,7 +29,7 @@
#include "radv_private.h" #include "radv_private.h"
bool bool
radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_stage, radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stage *fs_stage,
const struct radv_pipeline_key *key) const struct radv_pipeline_key *key)
{ {
const struct radv_shader_info *info = &fs_stage->info; const struct radv_shader_info *info = &fs_stage->info;

2
src/amd/vulkan/nir/radv_nir_lower_io.c
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@@ -103,7 +103,7 @@ radv_nir_lower_io(struct radv_device *device, nir_shader *nir)
} }
bool bool
radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *stage) radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *stage)
{ {
const struct radv_shader_info *info = &stage->info; const struct radv_shader_info *info = &stage->info;
nir_shader *nir = stage->nir; nir_shader *nir = stage->nir;

2
src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c
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@@ -416,7 +416,7 @@ lower_vs_input_instr(nir_builder *b, nir_instr *instr, void *state)
} }
bool bool
radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_pipeline_stage *vs_stage, radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_shader_stage *vs_stage,
const struct radv_pipeline_key *pl_key, const struct radeon_info *rad_info) const struct radv_pipeline_key *pl_key, const struct radeon_info *rad_info)
{ {
assert(shader->info.stage == MESA_SHADER_VERTEX); assert(shader->info.stage == MESA_SHADER_VERTEX);

4
src/amd/vulkan/radv_pipeline.c
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@@ -264,7 +264,7 @@ radv_get_hash_flags(const struct radv_device *device, bool stats)
} }
void void
radv_pipeline_stage_init(const VkPipelineShaderStageCreateInfo *sinfo, struct radv_pipeline_stage *out_stage, radv_shader_stage_init(const VkPipelineShaderStageCreateInfo *sinfo, struct radv_shader_stage *out_stage,
gl_shader_stage stage) gl_shader_stage stage)
{ {
const VkShaderModuleCreateInfo *minfo = vk_find_struct_const(sinfo->pNext, SHADER_MODULE_CREATE_INFO); const VkShaderModuleCreateInfo *minfo = vk_find_struct_const(sinfo->pNext, SHADER_MODULE_CREATE_INFO);
@@ -503,7 +503,7 @@ non_uniform_access_callback(const nir_src *src, void *_)
void void
radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout, radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_stage *stage) const struct radv_pipeline_key *pipeline_key, struct radv_shader_stage *stage)
{ {
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
bool progress; bool progress;

2
src/amd/vulkan/radv_pipeline_cache.c
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@@ -46,7 +46,7 @@ radv_is_cache_disabled(struct radv_device *device)
} }
void void
radv_hash_shaders(unsigned char *hash, const struct radv_pipeline_stage *stages, uint32_t stage_count, radv_hash_shaders(unsigned char *hash, const struct radv_shader_stage *stages, uint32_t stage_count,
const struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key, uint32_t flags) const struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key, uint32_t flags)
{ {
struct mesa_sha1 ctx; struct mesa_sha1 ctx;

6
src/amd/vulkan/radv_pipeline_compute.c
View File

@@ -127,7 +127,7 @@ radv_compute_pipeline_init(const struct radv_device *device, struct radv_compute
} }
static struct radv_shader * static struct radv_shader *
radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, struct radv_pipeline_stage *cs_stage, radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, struct radv_shader_stage *cs_stage,
const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_layout *pipeline_layout, const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_layout *pipeline_layout,
bool keep_executable_info, bool keep_statistic_info, bool is_internal, bool keep_executable_info, bool keep_statistic_info, bool is_internal,
struct radv_shader_binary **cs_binary) struct radv_shader_binary **cs_binary)
@@ -189,7 +189,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline, struct rad
unsigned char hash[20]; unsigned char hash[20];
bool keep_executable_info = radv_pipeline_capture_shaders(device, flags); bool keep_executable_info = radv_pipeline_capture_shaders(device, flags);
bool keep_statistic_info = radv_pipeline_capture_shader_stats(device, flags); bool keep_statistic_info = radv_pipeline_capture_shader_stats(device, flags);
struct radv_pipeline_stage cs_stage = {0}; struct radv_shader_stage cs_stage = {0};
VkPipelineCreationFeedback pipeline_feedback = { VkPipelineCreationFeedback pipeline_feedback = {
.flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT, .flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT,
}; };
@@ -197,7 +197,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline, struct rad
int64_t pipeline_start = os_time_get_nano(); int64_t pipeline_start = os_time_get_nano();
radv_pipeline_stage_init(pStage, &cs_stage, MESA_SHADER_COMPUTE); radv_shader_stage_init(pStage, &cs_stage, MESA_SHADER_COMPUTE);
radv_hash_shaders(hash, &cs_stage, 1, pipeline_layout, pipeline_key, radv_hash_shaders(hash, &cs_stage, 1, pipeline_layout, pipeline_key,
radv_get_hash_flags(device, keep_statistic_info)); radv_get_hash_flags(device, keep_statistic_info));

66
src/amd/vulkan/radv_pipeline_graphics.c
View File

@@ -1195,7 +1195,7 @@ get_vs_output_info(const struct radv_graphics_pipeline *pipeline)
} }
static bool static bool
radv_should_export_multiview(const struct radv_pipeline_stage *producer, const struct radv_pipeline_stage *consumer, radv_should_export_multiview(const struct radv_shader_stage *producer, const struct radv_shader_stage *consumer,
const struct radv_pipeline_key *pipeline_key) const struct radv_pipeline_key *pipeline_key)
{ {
/* Export the layer in the last VGT stage if multiview is used. When the next stage is unknown /* Export the layer in the last VGT stage if multiview is used. When the next stage is unknown
@@ -1434,8 +1434,8 @@ static const gl_shader_stage graphics_shader_order[] = {
}; };
static void static void
radv_link_vs(const struct radv_device *device, struct radv_pipeline_stage *vs_stage, radv_link_vs(const struct radv_device *device, struct radv_shader_stage *vs_stage, struct radv_shader_stage *next_stage,
struct radv_pipeline_stage *next_stage, const struct radv_pipeline_key *pipeline_key) const struct radv_pipeline_key *pipeline_key)
{ {
assert(vs_stage->nir->info.stage == MESA_SHADER_VERTEX); assert(vs_stage->nir->info.stage == MESA_SHADER_VERTEX);
@@ -1473,8 +1473,8 @@ radv_link_vs(const struct radv_device *device, struct radv_pipeline_stage *vs_st
} }
static void static void
radv_link_tcs(const struct radv_device *device, struct radv_pipeline_stage *tcs_stage, radv_link_tcs(const struct radv_device *device, struct radv_shader_stage *tcs_stage,
struct radv_pipeline_stage *tes_stage, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *tes_stage, const struct radv_pipeline_key *pipeline_key)
{ {
assert(tcs_stage->nir->info.stage == MESA_SHADER_TESS_CTRL); assert(tcs_stage->nir->info.stage == MESA_SHADER_TESS_CTRL);
assert(tes_stage->nir->info.stage == MESA_SHADER_TESS_EVAL); assert(tes_stage->nir->info.stage == MESA_SHADER_TESS_EVAL);
@@ -1495,8 +1495,8 @@ radv_link_tcs(const struct radv_device *device, struct radv_pipeline_stage *tcs_
} }
static void static void
radv_link_tes(const struct radv_device *device, struct radv_pipeline_stage *tes_stage, radv_link_tes(const struct radv_device *device, struct radv_shader_stage *tes_stage,
struct radv_pipeline_stage *next_stage, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *next_stage, const struct radv_pipeline_key *pipeline_key)
{ {
assert(tes_stage->nir->info.stage == MESA_SHADER_TESS_EVAL); assert(tes_stage->nir->info.stage == MESA_SHADER_TESS_EVAL);
@@ -1524,8 +1524,8 @@ radv_link_tes(const struct radv_device *device, struct radv_pipeline_stage *tes_
} }
static void static void
radv_link_gs(const struct radv_device *device, struct radv_pipeline_stage *gs_stage, radv_link_gs(const struct radv_device *device, struct radv_shader_stage *gs_stage, struct radv_shader_stage *fs_stage,
struct radv_pipeline_stage *fs_stage, const struct radv_pipeline_key *pipeline_key) const struct radv_pipeline_key *pipeline_key)
{ {
assert(gs_stage->nir->info.stage == MESA_SHADER_GEOMETRY); assert(gs_stage->nir->info.stage == MESA_SHADER_GEOMETRY);
@@ -1545,8 +1545,8 @@ radv_link_gs(const struct radv_device *device, struct radv_pipeline_stage *gs_st
} }
static void static void
radv_link_task(const struct radv_device *device, struct radv_pipeline_stage *task_stage, radv_link_task(const struct radv_device *device, struct radv_shader_stage *task_stage,
struct radv_pipeline_stage *mesh_stage, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *mesh_stage, const struct radv_pipeline_key *pipeline_key)
{ {
assert(task_stage->nir->info.stage == MESA_SHADER_TASK); assert(task_stage->nir->info.stage == MESA_SHADER_TASK);
assert(mesh_stage->nir->info.stage == MESA_SHADER_MESH); assert(mesh_stage->nir->info.stage == MESA_SHADER_MESH);
@@ -1556,8 +1556,8 @@ radv_link_task(const struct radv_device *device, struct radv_pipeline_stage *tas
} }
static void static void
radv_link_mesh(const struct radv_device *device, struct radv_pipeline_stage *mesh_stage, radv_link_mesh(const struct radv_device *device, struct radv_shader_stage *mesh_stage,
struct radv_pipeline_stage *fs_stage, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *fs_stage, const struct radv_pipeline_key *pipeline_key)
{ {
assert(mesh_stage->nir->info.stage == MESA_SHADER_MESH); assert(mesh_stage->nir->info.stage == MESA_SHADER_MESH);
@@ -1584,7 +1584,7 @@ radv_link_mesh(const struct radv_device *device, struct radv_pipeline_stage *mes
} }
static void static void
radv_link_fs(struct radv_pipeline_stage *fs_stage, const struct radv_pipeline_key *pipeline_key) radv_link_fs(struct radv_shader_stage *fs_stage, const struct radv_pipeline_key *pipeline_key)
{ {
assert(fs_stage->nir->info.stage == MESA_SHADER_FRAGMENT); assert(fs_stage->nir->info.stage == MESA_SHADER_FRAGMENT);
@@ -1637,10 +1637,10 @@ radv_remove_varyings(nir_shader *nir)
static void static void
radv_graphics_shaders_link(const struct radv_device *device, const struct radv_pipeline_key *pipeline_key, radv_graphics_shaders_link(const struct radv_device *device, const struct radv_pipeline_key *pipeline_key,
struct radv_pipeline_stage *stages) struct radv_shader_stage *stages)
{ {
/* Walk backwards to link */ /* Walk backwards to link */
struct radv_pipeline_stage *next_stage = NULL; struct radv_shader_stage *next_stage = NULL;
for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) { for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) {
gl_shader_stage s = graphics_shader_order[i]; gl_shader_stage s = graphics_shader_order[i];
if (!stages[s].nir) if (!stages[s].nir)
@@ -1988,7 +1988,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru
static void static void
radv_fill_shader_info_ngg(struct radv_device *device, const struct radv_pipeline_key *pipeline_key, radv_fill_shader_info_ngg(struct radv_device *device, const struct radv_pipeline_key *pipeline_key,
struct radv_pipeline_stage *stages, VkShaderStageFlagBits active_nir_stages) struct radv_shader_stage *stages, VkShaderStageFlagBits active_nir_stages)
{ {
if (pipeline_key->use_ngg) { if (pipeline_key->use_ngg) {
if (stages[MESA_SHADER_TESS_CTRL].nir) { if (stages[MESA_SHADER_TESS_CTRL].nir) {
@@ -2012,7 +2012,7 @@ radv_fill_shader_info_ngg(struct radv_device *device, const struct radv_pipeline
stages[MESA_SHADER_TESS_EVAL].info.is_ngg = false; stages[MESA_SHADER_TESS_EVAL].info.is_ngg = false;
} }
struct radv_pipeline_stage *last_vgt_stage = NULL; struct radv_shader_stage *last_vgt_stage = NULL;
radv_foreach_stage(i, active_nir_stages) radv_foreach_stage(i, active_nir_stages)
{ {
if (radv_is_last_vgt_stage(&stages[i])) { if (radv_is_last_vgt_stage(&stages[i])) {
@@ -2042,8 +2042,8 @@ radv_fill_shader_info_ngg(struct radv_device *device, const struct radv_pipeline
} }
static bool static bool
radv_consider_force_vrs(const struct radv_device *device, const struct radv_pipeline_stage *last_vgt_stage, radv_consider_force_vrs(const struct radv_device *device, const struct radv_shader_stage *last_vgt_stage,
const struct radv_pipeline_stage *fs_stage) const struct radv_shader_stage *fs_stage)
{ {
if (!device->force_vrs_enabled) if (!device->force_vrs_enabled)
return false; return false;
@@ -2116,7 +2116,7 @@ radv_get_next_stage(gl_shader_stage stage, VkShaderStageFlagBits active_nir_stag
static void static void
radv_fill_shader_info(struct radv_device *device, const enum radv_pipeline_type pipeline_type, radv_fill_shader_info(struct radv_device *device, const enum radv_pipeline_type pipeline_type,
struct radv_pipeline_layout *pipeline_layout, const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_layout *pipeline_layout, const struct radv_pipeline_key *pipeline_key,
struct radv_pipeline_stage *stages, VkShaderStageFlagBits active_nir_stages) struct radv_shader_stage *stages, VkShaderStageFlagBits active_nir_stages)
{ {
radv_foreach_stage(i, active_nir_stages) radv_foreach_stage(i, active_nir_stages)
{ {
@@ -2134,7 +2134,7 @@ radv_fill_shader_info(struct radv_device *device, const enum radv_pipeline_type
} }
static void static void
radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stage *stages, radv_declare_pipeline_args(struct radv_device *device, struct radv_shader_stage *stages,
const struct radv_pipeline_key *pipeline_key, VkShaderStageFlagBits active_nir_stages) const struct radv_pipeline_key *pipeline_key, VkShaderStageFlagBits active_nir_stages)
{ {
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
@@ -2179,7 +2179,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
static struct radv_shader * static struct radv_shader *
radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache *cache, radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache *cache,
struct radv_pipeline_stage *gs_stage, const struct radv_pipeline_key *pipeline_key, struct radv_shader_stage *gs_stage, const struct radv_pipeline_key *pipeline_key,
const struct radv_pipeline_layout *pipeline_layout, bool keep_executable_info, const struct radv_pipeline_layout *pipeline_layout, bool keep_executable_info,
bool keep_statistic_info, struct radv_shader_binary **gs_copy_binary) bool keep_statistic_info, struct radv_shader_binary **gs_copy_binary)
{ {
@@ -2196,7 +2196,7 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache
nir_validate_shader(nir, "after ac_nir_create_gs_copy_shader"); nir_validate_shader(nir, "after ac_nir_create_gs_copy_shader");
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
struct radv_pipeline_stage gs_copy_stage = { struct radv_shader_stage gs_copy_stage = {
.stage = MESA_SHADER_VERTEX, .stage = MESA_SHADER_VERTEX,
.shader_sha1 = {0}, .shader_sha1 = {0},
}; };
@@ -2237,7 +2237,7 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache
static void static void
radv_pipeline_nir_to_asm(struct radv_device *device, struct radv_graphics_pipeline *pipeline, radv_pipeline_nir_to_asm(struct radv_device *device, struct radv_graphics_pipeline *pipeline,
struct vk_pipeline_cache *cache, struct radv_pipeline_stage *stages, struct vk_pipeline_cache *cache, struct radv_shader_stage *stages,
const struct radv_pipeline_key *pipeline_key, const struct radv_pipeline_key *pipeline_key,
const struct radv_pipeline_layout *pipeline_layout, bool keep_executable_info, const struct radv_pipeline_layout *pipeline_layout, bool keep_executable_info,
bool keep_statistic_info, VkShaderStageFlagBits active_nir_stages, bool keep_statistic_info, VkShaderStageFlagBits active_nir_stages,
@@ -2292,7 +2292,7 @@ radv_pipeline_nir_to_asm(struct radv_device *device, struct radv_graphics_pipeli
static void static void
radv_pipeline_get_nir(struct radv_device *device, struct radv_graphics_pipeline *pipeline, radv_pipeline_get_nir(struct radv_device *device, struct radv_graphics_pipeline *pipeline,
struct radv_pipeline_stage *stages, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *stages, const struct radv_pipeline_key *pipeline_key)
{ {
for (unsigned s = 0; s < MESA_VULKAN_SHADER_STAGES; s++) { for (unsigned s = 0; s < MESA_VULKAN_SHADER_STAGES; s++) {
if (!stages[s].entrypoint) if (!stages[s].entrypoint)
@@ -2310,7 +2310,7 @@ radv_pipeline_get_nir(struct radv_device *device, struct radv_graphics_pipeline
} }
static void static void
radv_pipeline_retain_shaders(struct radv_graphics_lib_pipeline *gfx_pipeline_lib, struct radv_pipeline_stage *stages) radv_pipeline_retain_shaders(struct radv_graphics_lib_pipeline *gfx_pipeline_lib, struct radv_shader_stage *stages)
{ {
for (unsigned s = 0; s < MESA_VULKAN_SHADER_STAGES; s++) { for (unsigned s = 0; s < MESA_VULKAN_SHADER_STAGES; s++) {
if (!stages[s].entrypoint) if (!stages[s].entrypoint)
@@ -2334,7 +2334,7 @@ radv_pipeline_retain_shaders(struct radv_graphics_lib_pipeline *gfx_pipeline_lib
static void static void
radv_pipeline_import_retained_shaders(const struct radv_device *device, struct radv_graphics_pipeline *pipeline, radv_pipeline_import_retained_shaders(const struct radv_device *device, struct radv_graphics_pipeline *pipeline,
struct radv_graphics_lib_pipeline *lib, struct radv_pipeline_stage *stages) struct radv_graphics_lib_pipeline *lib, struct radv_shader_stage *stages)
{ {
/* Import the stages (SPIR-V only in case of cache hits). */ /* Import the stages (SPIR-V only in case of cache hits). */
for (uint32_t i = 0; i < lib->stage_count; i++) { for (uint32_t i = 0; i < lib->stage_count; i++) {
@@ -2345,7 +2345,7 @@ radv_pipeline_import_retained_shaders(const struct radv_device *device, struct r
if (!(shader_stage_to_pipeline_library_flags(sinfo->stage) & lib->lib_flags)) if (!(shader_stage_to_pipeline_library_flags(sinfo->stage) & lib->lib_flags))
continue; continue;
radv_pipeline_stage_init(sinfo, &stages[s], s); radv_shader_stage_init(sinfo, &stages[s], s);
} }
/* Import the NIR shaders (after SPIRV->NIR). */ /* Import the NIR shaders (after SPIRV->NIR). */
@@ -2374,7 +2374,7 @@ radv_pipeline_import_retained_shaders(const struct radv_device *device, struct r
static void static void
radv_pipeline_load_retained_shaders(const struct radv_device *device, struct radv_graphics_pipeline *pipeline, radv_pipeline_load_retained_shaders(const struct radv_device *device, struct radv_graphics_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo, struct radv_pipeline_stage *stages) const VkGraphicsPipelineCreateInfo *pCreateInfo, struct radv_shader_stage *stages)
{ {
const VkPipelineLibraryCreateInfoKHR *libs_info = const VkPipelineLibraryCreateInfoKHR *libs_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_LIBRARY_CREATE_INFO_KHR); vk_find_struct_const(pCreateInfo->pNext, PIPELINE_LIBRARY_CREATE_INFO_KHR);
@@ -2427,7 +2427,7 @@ radv_pipeline_create_ps_epilog(struct radv_device *device, struct radv_graphics_
} }
static unsigned static unsigned
radv_get_rasterization_prim(const struct radv_pipeline_stage *stages, const struct radv_pipeline_key *pipeline_key) radv_get_rasterization_prim(const struct radv_shader_stage *stages, const struct radv_pipeline_key *pipeline_key)
{ {
unsigned rast_prim; unsigned rast_prim;
@@ -2512,7 +2512,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
unsigned char hash[20]; unsigned char hash[20];
bool keep_executable_info = radv_pipeline_capture_shaders(device, pCreateInfo->flags); bool keep_executable_info = radv_pipeline_capture_shaders(device, pCreateInfo->flags);
bool keep_statistic_info = radv_pipeline_capture_shader_stats(device, pCreateInfo->flags); bool keep_statistic_info = radv_pipeline_capture_shader_stats(device, pCreateInfo->flags);
struct radv_pipeline_stage stages[MESA_VULKAN_SHADER_STAGES]; struct radv_shader_stage stages[MESA_VULKAN_SHADER_STAGES];
const VkPipelineCreationFeedbackCreateInfo *creation_feedback = const VkPipelineCreationFeedbackCreateInfo *creation_feedback =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO); vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO);
VkPipelineCreationFeedback pipeline_feedback = { VkPipelineCreationFeedback pipeline_feedback = {
@@ -2538,7 +2538,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
if (!(shader_stage_to_pipeline_library_flags(sinfo->stage) & lib_flags)) if (!(shader_stage_to_pipeline_library_flags(sinfo->stage) & lib_flags))
continue; continue;
radv_pipeline_stage_init(sinfo, &stages[stage], stage); radv_shader_stage_init(sinfo, &stages[stage], stage);
} }
radv_pipeline_load_retained_shaders(device, pipeline, pCreateInfo, stages); radv_pipeline_load_retained_shaders(device, pipeline, pCreateInfo, stages);

14
src/amd/vulkan/radv_pipeline_rt.c
View File

@@ -255,8 +255,8 @@ radv_rt_fill_stage_info(struct radv_device *device, const VkRayTracingPipelineCr
for (idx = 0; idx < pCreateInfo->stageCount; idx++) { for (idx = 0; idx < pCreateInfo->stageCount; idx++) {
stages[idx].stage = vk_to_mesa_shader_stage(pCreateInfo->pStages[idx].stage); stages[idx].stage = vk_to_mesa_shader_stage(pCreateInfo->pStages[idx].stage);
struct radv_pipeline_stage stage; struct radv_shader_stage stage;
radv_pipeline_stage_init(&pCreateInfo->pStages[idx], &stage, stages[idx].stage); radv_shader_stage_init(&pCreateInfo->pStages[idx], &stage, stages[idx].stage);
radv_hash_shaders(stages[idx].sha1, &stage, 1, NULL, key, radv_get_hash_flags(device, false)); radv_hash_shaders(stages[idx].sha1, &stage, 1, NULL, key, radv_get_hash_flags(device, false));
} }
@@ -342,7 +342,7 @@ move_rt_instructions(nir_shader *shader)
static VkResult static VkResult
radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, const struct radv_pipeline_key *pipeline_key, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, const struct radv_pipeline_key *pipeline_key,
struct radv_pipeline_stage *stage, uint32_t *stack_size, struct radv_shader_stage *stage, uint32_t *stack_size,
struct radv_serialized_shader_arena_block *replay_block, struct radv_shader **out_shader) struct radv_serialized_shader_arena_block *replay_block, struct radv_shader **out_shader)
{ {
struct radv_shader_binary *binary; struct radv_shader_binary *binary;
@@ -387,7 +387,7 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache,
/* Postprocess shader parts. */ /* Postprocess shader parts. */
for (uint32_t i = 0; i < num_shaders; i++) { for (uint32_t i = 0; i < num_shaders; i++) {
struct radv_pipeline_stage temp_stage = *stage; struct radv_shader_stage temp_stage = *stage;
temp_stage.nir = shaders[i]; temp_stage.nir = shaders[i];
radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, &stage->info, stack_size, i > 0); radv_nir_lower_rt_abi(temp_stage.nir, pCreateInfo, &temp_stage.args, &stage->info, stack_size, i > 0);
radv_optimize_nir(temp_stage.nir, pipeline_key->optimisations_disabled); radv_optimize_nir(temp_stage.nir, pipeline_key->optimisations_disabled);
@@ -444,8 +444,8 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca
for (uint32_t idx = 0; idx < pCreateInfo->stageCount; idx++) { for (uint32_t idx = 0; idx < pCreateInfo->stageCount; idx++) {
int64_t stage_start = os_time_get_nano(); int64_t stage_start = os_time_get_nano();
struct radv_pipeline_stage stage; struct radv_shader_stage stage;
radv_pipeline_stage_init(&pCreateInfo->pStages[idx], &stage, stages[idx].stage); radv_shader_stage_init(&pCreateInfo->pStages[idx], &stage, stages[idx].stage);
if (stages[idx].shader) if (stages[idx].shader)
goto feedback; goto feedback;
@@ -495,7 +495,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca
.module = vk_shader_module_to_handle(&traversal_module), .module = vk_shader_module_to_handle(&traversal_module),
.pName = "main", .pName = "main",
}; };
struct radv_pipeline_stage traversal_stage = { struct radv_shader_stage traversal_stage = {
.stage = MESA_SHADER_INTERSECTION, .stage = MESA_SHADER_INTERSECTION,
.nir = traversal_module.nir, .nir = traversal_module.nir,
}; };

10
src/amd/vulkan/radv_private.h
View File

@@ -2126,10 +2126,10 @@ struct radv_event {
struct radv_pipeline_key; struct radv_pipeline_key;
struct radv_ray_tracing_group; struct radv_ray_tracing_group;
void radv_pipeline_stage_init(const VkPipelineShaderStageCreateInfo *sinfo, struct radv_pipeline_stage *out_stage, void radv_shader_stage_init(const VkPipelineShaderStageCreateInfo *sinfo, struct radv_shader_stage *out_stage,
gl_shader_stage stage); gl_shader_stage stage);
void radv_hash_shaders(unsigned char *hash, const struct radv_pipeline_stage *stages, uint32_t stage_count, void radv_hash_shaders(unsigned char *hash, const struct radv_shader_stage *stages, uint32_t stage_count,
const struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key, uint32_t flags); const struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key, uint32_t flags);
void radv_hash_rt_stages(struct mesa_sha1 *ctx, const VkPipelineShaderStageCreateInfo *stages, unsigned stage_count); void radv_hash_rt_stages(struct mesa_sha1 *ctx, const VkPipelineShaderStageCreateInfo *stages, unsigned stage_count);
@@ -2386,7 +2386,7 @@ RADV_DECL_PIPELINE_DOWNCAST(graphics_lib, RADV_PIPELINE_GRAPHICS_LIB)
RADV_DECL_PIPELINE_DOWNCAST(compute, RADV_PIPELINE_COMPUTE) RADV_DECL_PIPELINE_DOWNCAST(compute, RADV_PIPELINE_COMPUTE)
RADV_DECL_PIPELINE_DOWNCAST(ray_tracing, RADV_PIPELINE_RAY_TRACING) RADV_DECL_PIPELINE_DOWNCAST(ray_tracing, RADV_PIPELINE_RAY_TRACING)
struct radv_pipeline_stage { struct radv_shader_stage {
gl_shader_stage stage; gl_shader_stage stage;
struct { struct {
@@ -2410,7 +2410,7 @@ struct radv_pipeline_stage {
}; };
static inline bool static inline bool
radv_is_last_vgt_stage(const struct radv_pipeline_stage *stage) radv_is_last_vgt_stage(const struct radv_shader_stage *stage)
{ {
return (stage->info.stage == MESA_SHADER_VERTEX || stage->info.stage == MESA_SHADER_TESS_EVAL || return (stage->info.stage == MESA_SHADER_VERTEX || stage->info.stage == MESA_SHADER_TESS_EVAL ||
stage->info.stage == MESA_SHADER_GEOMETRY || stage->info.stage == MESA_SHADER_MESH) && stage->info.stage == MESA_SHADER_GEOMETRY || stage->info.stage == MESA_SHADER_MESH) &&
@@ -3041,7 +3041,7 @@ void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shad
void radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info); void radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info);
void radv_nir_shader_info_link(struct radv_device *device, const struct radv_pipeline_key *pipeline_key, void radv_nir_shader_info_link(struct radv_device *device, const struct radv_pipeline_key *pipeline_key,
struct radv_pipeline_stage *stages); struct radv_shader_stage *stages);
bool radv_sqtt_init(struct radv_device *device); bool radv_sqtt_init(struct radv_device *device);
void radv_sqtt_finish(struct radv_device *device); void radv_sqtt_finish(struct radv_device *device);

4
src/amd/vulkan/radv_rt_shader.c
View File

@@ -813,9 +813,9 @@ nir_shader *
radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *sinfo, radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *sinfo,
const struct radv_pipeline_key *key) const struct radv_pipeline_key *key)
{ {
struct radv_pipeline_stage rt_stage; struct radv_shader_stage rt_stage;
radv_pipeline_stage_init(sinfo, &rt_stage, vk_to_mesa_shader_stage(sinfo->stage)); radv_shader_stage_init(sinfo, &rt_stage, vk_to_mesa_shader_stage(sinfo->stage));
nir_shader *shader = radv_shader_spirv_to_nir(device, &rt_stage, key, false); nir_shader *shader = radv_shader_spirv_to_nir(device, &rt_stage, key, false);

7
src/amd/vulkan/radv_shader.c
View File

@@ -326,7 +326,7 @@ is_not_xfb_output(nir_variable *var, void *data)
} }
nir_shader * nir_shader *
radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_stage *stage, radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_stage *stage,
const struct radv_pipeline_key *key, bool is_internal) const struct radv_pipeline_key *key, bool is_internal)
{ {
unsigned subgroup_size = 64, ballot_bit_size = 64; unsigned subgroup_size = 64, ballot_bit_size = 64;
@@ -809,8 +809,7 @@ setup_ngg_lds_layout(struct radv_device *device, nir_shader *nir, struct radv_sh
} }
void void
radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_stage, radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage, const struct radv_pipeline_key *pl_key)
const struct radv_pipeline_key *pl_key)
{ {
const struct radv_shader_info *info = &ngg_stage->info; const struct radv_shader_info *info = &ngg_stage->info;
nir_shader *nir = ngg_stage->nir; nir_shader *nir = ngg_stage->nir;
@@ -2349,7 +2348,7 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in
} }
struct radv_shader_binary * struct radv_shader_binary *
radv_shader_nir_to_asm(struct radv_device *device, struct radv_pipeline_stage *pl_stage, radv_shader_nir_to_asm(struct radv_device *device, struct radv_shader_stage *pl_stage,
struct nir_shader *const *shaders, int shader_count, const struct radv_pipeline_key *key, struct nir_shader *const *shaders, int shader_count, const struct radv_pipeline_key *key,
bool keep_shader_info, bool keep_statistic_info) bool keep_shader_info, bool keep_statistic_info)
{ {

12
src/amd/vulkan/radv_shader.h
View File

@@ -597,13 +597,13 @@ struct radv_shader_part {
}; };
struct radv_pipeline_layout; struct radv_pipeline_layout;
struct radv_pipeline_stage; struct radv_shader_stage;
void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively); void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
void radv_optimize_nir_algebraic(nir_shader *shader, bool opt_offsets); void radv_optimize_nir_algebraic(nir_shader *shader, bool opt_offsets);
void radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout, void radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
const struct radv_pipeline_key *pipeline_key, struct radv_pipeline_stage *stage); const struct radv_pipeline_key *pipeline_key, struct radv_shader_stage *stage);
nir_shader *radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *sinfo, nir_shader *radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *sinfo,
const struct radv_pipeline_key *key); const struct radv_pipeline_key *key);
@@ -612,9 +612,9 @@ void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateI
const struct radv_shader_args *args, const struct radv_shader_info *info, const struct radv_shader_args *args, const struct radv_shader_info *info,
uint32_t *stack_size, bool resume_shader); uint32_t *stack_size, bool resume_shader);
struct radv_pipeline_stage; struct radv_shader_stage;
nir_shader *radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_stage *stage, nir_shader *radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_stage *stage,
const struct radv_pipeline_key *key, bool is_internal); const struct radv_pipeline_key *key, bool is_internal);
void radv_init_shader_arenas(struct radv_device *device); void radv_init_shader_arenas(struct radv_device *device);
@@ -631,7 +631,7 @@ VkResult radv_shader_create_uncached(struct radv_device *device, const struct ra
bool replayable, struct radv_serialized_shader_arena_block *replay_block, bool replayable, struct radv_serialized_shader_arena_block *replay_block,
struct radv_shader **out_shader); struct radv_shader **out_shader);
struct radv_shader_binary *radv_shader_nir_to_asm(struct radv_device *device, struct radv_pipeline_stage *pl_stage, struct radv_shader_binary *radv_shader_nir_to_asm(struct radv_device *device, struct radv_shader_stage *pl_stage,
struct nir_shader *const *shaders, int shader_count, struct nir_shader *const *shaders, int shader_count,
const struct radv_pipeline_key *key, bool keep_shader_info, const struct radv_pipeline_key *key, bool keep_shader_info,
bool keep_statistic_info); bool keep_statistic_info);
@@ -817,7 +817,7 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_ver
return num_patches; return num_patches;
} }
void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_stage, void radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage,
const struct radv_pipeline_key *pl_key); const struct radv_pipeline_key *pl_key);
bool radv_consider_culling(const struct radv_physical_device *pdevice, struct nir_shader *nir, uint64_t ps_inputs_read, bool radv_consider_culling(const struct radv_physical_device *pdevice, struct nir_shader *nir, uint64_t ps_inputs_read,

40
src/amd/vulkan/radv_shader_info.c
View File

@@ -1066,8 +1066,8 @@ radv_init_legacy_gs_ring_info(const struct radv_device *device, struct radv_shad
} }
static void static void
radv_get_legacy_gs_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage, radv_get_legacy_gs_info(const struct radv_device *device, struct radv_shader_stage *es_stage,
struct radv_pipeline_stage *gs_stage) struct radv_shader_stage *gs_stage)
{ {
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
struct radv_shader_info *gs_info = &gs_stage->info; struct radv_shader_info *gs_info = &gs_stage->info;
@@ -1185,7 +1185,7 @@ clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts, unsigned m
} }
static unsigned static unsigned
radv_get_num_input_vertices(const struct radv_pipeline_stage *es_stage, const struct radv_pipeline_stage *gs_stage) radv_get_num_input_vertices(const struct radv_shader_stage *es_stage, const struct radv_shader_stage *gs_stage)
{ {
if (gs_stage) { if (gs_stage) {
return gs_stage->nir->info.gs.vertices_in; return gs_stage->nir->info.gs.vertices_in;
@@ -1203,7 +1203,7 @@ radv_get_num_input_vertices(const struct radv_pipeline_stage *es_stage, const st
} }
static unsigned static unsigned
radv_get_pre_rast_input_topology(const struct radv_pipeline_stage *es_stage, const struct radv_pipeline_stage *gs_stage) radv_get_pre_rast_input_topology(const struct radv_shader_stage *es_stage, const struct radv_shader_stage *gs_stage)
{ {
if (gs_stage) { if (gs_stage) {
return gs_stage->nir->info.gs.input_primitive; return gs_stage->nir->info.gs.input_primitive;
@@ -1221,8 +1221,8 @@ radv_get_pre_rast_input_topology(const struct radv_pipeline_stage *es_stage, con
} }
static void static void
gfx10_get_ngg_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage, gfx10_get_ngg_info(const struct radv_device *device, struct radv_shader_stage *es_stage,
struct radv_pipeline_stage *gs_stage) struct radv_shader_stage *gs_stage)
{ {
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
struct radv_shader_info *gs_info = gs_stage ? &gs_stage->info : NULL; struct radv_shader_info *gs_info = gs_stage ? &gs_stage->info : NULL;
@@ -1442,8 +1442,8 @@ gfx10_get_ngg_info(const struct radv_device *device, struct radv_pipeline_stage
} }
static void static void
gfx10_get_ngg_query_info(const struct radv_device *device, struct radv_pipeline_stage *es_stage, gfx10_get_ngg_query_info(const struct radv_device *device, struct radv_shader_stage *es_stage,
struct radv_pipeline_stage *gs_stage, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *gs_stage, const struct radv_pipeline_key *pipeline_key)
{ {
struct radv_shader_info *info = gs_stage ? &gs_stage->info : &es_stage->info; struct radv_shader_info *info = gs_stage ? &gs_stage->info : &es_stage->info;
@@ -1453,8 +1453,8 @@ gfx10_get_ngg_query_info(const struct radv_device *device, struct radv_pipeline_
} }
static void static void
radv_determine_ngg_settings(struct radv_device *device, struct radv_pipeline_stage *es_stage, radv_determine_ngg_settings(struct radv_device *device, struct radv_shader_stage *es_stage,
struct radv_pipeline_stage *fs_stage, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *fs_stage, const struct radv_pipeline_key *pipeline_key)
{ {
assert(es_stage->stage == MESA_SHADER_VERTEX || es_stage->stage == MESA_SHADER_TESS_EVAL); assert(es_stage->stage == MESA_SHADER_VERTEX || es_stage->stage == MESA_SHADER_TESS_EVAL);
assert(!fs_stage || fs_stage->stage == MESA_SHADER_FRAGMENT); assert(!fs_stage || fs_stage->stage == MESA_SHADER_FRAGMENT);
@@ -1486,8 +1486,8 @@ radv_determine_ngg_settings(struct radv_device *device, struct radv_pipeline_sta
} }
static void static void
radv_link_shaders_info(struct radv_device *device, struct radv_pipeline_stage *producer, radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *producer,
struct radv_pipeline_stage *consumer, const struct radv_pipeline_key *pipeline_key) struct radv_shader_stage *consumer, const struct radv_pipeline_key *pipeline_key)
{ {
/* Export primitive ID and clip/cull distances if read by the FS, or export unconditionally when /* Export primitive ID and clip/cull distances if read by the FS, or export unconditionally when
* the next stage is unknown (with graphics pipeline library). * the next stage is unknown (with graphics pipeline library).
@@ -1519,7 +1519,7 @@ radv_link_shaders_info(struct radv_device *device, struct radv_pipeline_stage *p
if (producer->stage == MESA_SHADER_VERTEX || producer->stage == MESA_SHADER_TESS_EVAL) { if (producer->stage == MESA_SHADER_VERTEX || producer->stage == MESA_SHADER_TESS_EVAL) {
/* Compute NGG info (GFX10+) or GS info. */ /* Compute NGG info (GFX10+) or GS info. */
if (producer->info.is_ngg) { if (producer->info.is_ngg) {
struct radv_pipeline_stage *gs_stage = consumer && consumer->stage == MESA_SHADER_GEOMETRY ? consumer : NULL; struct radv_shader_stage *gs_stage = consumer && consumer->stage == MESA_SHADER_GEOMETRY ? consumer : NULL;
gfx10_get_ngg_info(device, producer, gs_stage); gfx10_get_ngg_info(device, producer, gs_stage);
gfx10_get_ngg_query_info(device, producer, gs_stage, pipeline_key); gfx10_get_ngg_query_info(device, producer, gs_stage, pipeline_key);
@@ -1534,8 +1534,8 @@ radv_link_shaders_info(struct radv_device *device, struct radv_pipeline_stage *p
} }
if (producer->stage == MESA_SHADER_VERTEX && consumer && consumer->stage == MESA_SHADER_TESS_CTRL) { if (producer->stage == MESA_SHADER_VERTEX && consumer && consumer->stage == MESA_SHADER_TESS_CTRL) {
struct radv_pipeline_stage *vs_stage = producer; struct radv_shader_stage *vs_stage = producer;
struct radv_pipeline_stage *tcs_stage = consumer; struct radv_shader_stage *tcs_stage = consumer;
if (pipeline_key->dynamic_patch_control_points) { if (pipeline_key->dynamic_patch_control_points) {
/* Set the workgroup size to the maximum possible value to ensure that compilers don't /* Set the workgroup size to the maximum possible value to ensure that compilers don't
@@ -1578,8 +1578,8 @@ radv_link_shaders_info(struct radv_device *device, struct radv_pipeline_stage *p
/* Copy shader info between TCS<->TES. */ /* Copy shader info between TCS<->TES. */
if (producer->stage == MESA_SHADER_TESS_CTRL) { if (producer->stage == MESA_SHADER_TESS_CTRL) {
struct radv_pipeline_stage *tcs_stage = producer; struct radv_shader_stage *tcs_stage = producer;
struct radv_pipeline_stage *tes_stage = consumer; struct radv_shader_stage *tes_stage = consumer;
tcs_stage->info.tcs.tes_reads_tess_factors = tcs_stage->info.tcs.tes_reads_tess_factors =
!!(tes_stage->nir->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER)); !!(tes_stage->nir->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
@@ -1596,7 +1596,7 @@ radv_link_shaders_info(struct radv_device *device, struct radv_pipeline_stage *p
} }
static void static void
radv_nir_shader_info_merge(const struct radv_pipeline_stage *src, struct radv_pipeline_stage *dst) radv_nir_shader_info_merge(const struct radv_shader_stage *src, struct radv_shader_stage *dst)
{ {
const struct radv_shader_info *src_info = &src->info; const struct radv_shader_info *src_info = &src->info;
struct radv_shader_info *dst_info = &dst->info; struct radv_shader_info *dst_info = &dst->info;
@@ -1634,10 +1634,10 @@ static const gl_shader_stage graphics_shader_order[] = {
void void
radv_nir_shader_info_link(struct radv_device *device, const struct radv_pipeline_key *pipeline_key, radv_nir_shader_info_link(struct radv_device *device, const struct radv_pipeline_key *pipeline_key,
struct radv_pipeline_stage *stages) struct radv_shader_stage *stages)
{ {
/* Walk backwards to link */ /* Walk backwards to link */
struct radv_pipeline_stage *next_stage = stages[MESA_SHADER_FRAGMENT].nir ? &stages[MESA_SHADER_FRAGMENT] : NULL; struct radv_shader_stage *next_stage = stages[MESA_SHADER_FRAGMENT].nir ? &stages[MESA_SHADER_FRAGMENT] : NULL;
for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) { for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) {
gl_shader_stage s = graphics_shader_order[i]; gl_shader_stage s = graphics_shader_order[i];