From 07eba9a15a06ceda3469892822e8b539effc6788 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 16 May 2022 16:42:22 +0200 Subject: [PATCH] radv: do not lower loading TESS/ESGS rings using the ABI for LLVM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LLVM uses an implicit argument for the ring offsets and this lowering was just broken. This fixes tessellation and geometry on all generations with LLVM. Fixes: 896a55f47d9 ("radv: Lower ABI in NIR for tess/ESGS/NGG shader arguments.") Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 3 +++ src/amd/vulkan/radv_nir_lower_abi.c | 12 ++++++++---- src/amd/vulkan/radv_nir_to_llvm.c | 8 ++++++++ src/amd/vulkan/radv_pipeline.c | 3 ++- src/amd/vulkan/radv_shader.h | 2 +- 5 files changed, 22 insertions(+), 6 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 58f5402d0bd..875708ca9ef 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3623,6 +3623,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_tess_level_inner_default: case nir_intrinsic_load_patch_vertices_in: case nir_intrinsic_load_sample_mask_in: + case nir_intrinsic_load_ring_tess_factors_amd: + case nir_intrinsic_load_ring_tess_offchip_amd: + case nir_intrinsic_load_ring_esgs_amd: result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic); break; case nir_intrinsic_load_vertex_id: diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index 3b5cdd8a296..f89f4f6065c 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -34,6 +34,7 @@ typedef struct { const struct radv_shader_args *args; const struct radv_shader_info *info; const struct radv_pipeline_key *pl_key; + bool use_llvm; } lower_abi_state; static nir_ssa_def * @@ -190,17 +191,19 @@ static bool filter_abi_instr(const nir_instr *instr, UNUSED const void *state) { + lower_abi_state *s = (lower_abi_state *) state; + if (instr->type != nir_instr_type_intrinsic) return false; nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - return intrin->intrinsic == nir_intrinsic_load_ring_tess_factors_amd || + return (intrin->intrinsic == nir_intrinsic_load_ring_tess_factors_amd && !s->use_llvm) || + (intrin->intrinsic == nir_intrinsic_load_ring_tess_offchip_amd && !s->use_llvm) || + (intrin->intrinsic == nir_intrinsic_load_ring_esgs_amd && !s->use_llvm) || intrin->intrinsic == nir_intrinsic_load_ring_tess_factors_offset_amd || - intrin->intrinsic == nir_intrinsic_load_ring_tess_offchip_amd || intrin->intrinsic == nir_intrinsic_load_ring_tess_offchip_offset_amd || intrin->intrinsic == nir_intrinsic_load_patch_vertices_in || intrin->intrinsic == nir_intrinsic_load_tcs_num_patches_amd || - intrin->intrinsic == nir_intrinsic_load_ring_esgs_amd || intrin->intrinsic == nir_intrinsic_load_ring_es2gs_offset_amd || intrin->intrinsic == nir_intrinsic_load_tess_rel_patch_id_amd || intrin->intrinsic == nir_intrinsic_load_gs_vertex_offset_amd || @@ -228,13 +231,14 @@ filter_abi_instr(const nir_instr *instr, void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_info *info, const struct radv_shader_args *args, - const struct radv_pipeline_key *pl_key) + const struct radv_pipeline_key *pl_key, bool use_llvm) { lower_abi_state state = { .gfx_level = gfx_level, .info = info, .args = args, .pl_key = pl_key, + .use_llvm = use_llvm, }; nir_shader_lower_instructions(shader, filter_abi_instr, lower_abi_instr, &state); diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 064287e3bdc..ed7a3ec7a73 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -2014,10 +2014,18 @@ declare_esgs_ring(struct radv_shader_context *ctx) static LLVMValueRef radv_intrinsic_load(struct ac_shader_abi *abi, nir_intrinsic_op op) { + struct radv_shader_context *ctx = radv_shader_context_from_abi(abi); + switch (op) { case nir_intrinsic_load_base_vertex: case nir_intrinsic_load_first_vertex: return radv_load_base_vertex(abi, op == nir_intrinsic_load_base_vertex); + case nir_intrinsic_load_ring_tess_factors_amd: + return ctx->hs_ring_tess_factor; + case nir_intrinsic_load_ring_tess_offchip_amd: + return ctx->hs_ring_tess_offchip; + case nir_intrinsic_load_ring_esgs_amd: + return ctx->esgs_ring; default: return NULL; } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 569740b9cd0..1d400ff07ae 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4552,7 +4552,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout ac_nir_lower_global_access(stages[i].nir); radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.gfx_level, - &stages[i].info, &stages[i].args, pipeline_key); + &stages[i].info, &stages[i].args, pipeline_key, + radv_use_llvm_for_stage(device, i)); radv_optimize_nir_algebraic( stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE || i == MESA_SHADER_TASK); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 4add8b598d6..f47205eda83 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -527,7 +527,7 @@ nir_shader *radv_shader_compile_to_nir(struct radv_device *device, void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_info *info, const struct radv_shader_args *args, - const struct radv_pipeline_key *pl_key); + const struct radv_pipeline_key *pl_key, bool use_llvm); void radv_init_shader_arenas(struct radv_device *device); void radv_destroy_shader_arenas(struct radv_device *device);