From 07afc7e3ed21a2be22d4486b3d85033cdc3b3d93 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 23 Apr 2024 11:34:17 +0200 Subject: [PATCH] panvk: Fully transition to vk_rasterization_state There's no point storing the rasterizer state twice. Use vk_rasterization_state everywhere, and let the core implement CmdSetLineWidth() and CmdSetDepthBias() for us. Signed-off-by: Boris Brezillon Reviewed-by: Mary Guillemard Acked-by: Erik Faye-Lund Part-of: --- src/panfrost/vulkan/panvk_cmd_buffer.h | 11 ---- src/panfrost/vulkan/panvk_pipeline.h | 15 ------ src/panfrost/vulkan/panvk_vX_cmd_buffer.c | 64 ++++++++--------------- src/panfrost/vulkan/panvk_vX_pipeline.c | 56 ++++++-------------- 4 files changed, 38 insertions(+), 108 deletions(-) diff --git a/src/panfrost/vulkan/panvk_cmd_buffer.h b/src/panfrost/vulkan/panvk_cmd_buffer.h index 7d2fd5c2dad..11205a54cb8 100644 --- a/src/panfrost/vulkan/panvk_cmd_buffer.h +++ b/src/panfrost/vulkan/panvk_cmd_buffer.h @@ -73,8 +73,6 @@ struct panvk_cmd_event_op { }; enum panvk_dynamic_state_bits { - PANVK_DYNAMIC_LINE_WIDTH = 1 << 2, - PANVK_DYNAMIC_DEPTH_BIAS = 1 << 3, PANVK_DYNAMIC_BLEND_CONSTANTS = 1 << 4, PANVK_DYNAMIC_DEPTH_BOUNDS = 1 << 5, PANVK_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, @@ -127,15 +125,6 @@ struct panvk_cmd_graphics_state { float constants[4]; } blend; - struct { - struct { - float constant_factor; - float clamp; - float slope_factor; - } depth_bias; - float line_width; - } rast; - struct { struct panvk_attrib_buf bufs[MAX_VBS]; unsigned count; diff --git a/src/panfrost/vulkan/panvk_pipeline.h b/src/panfrost/vulkan/panvk_pipeline.h index 33bf4b293ae..0d362baffdd 100644 --- a/src/panfrost/vulkan/panvk_pipeline.h +++ b/src/panfrost/vulkan/panvk_pipeline.h @@ -98,21 +98,6 @@ struct panvk_graphics_pipeline { bool primitive_restart; } ia; - struct { - bool clamp_depth; - float line_width; - struct { - bool enable; - float constant_factor; - float clamp; - float slope_factor; - } depth_bias; - bool front_ccw; - bool cull_front_face; - bool cull_back_face; - bool enable; - } rast; - struct { bool z_test; bool z_write; diff --git a/src/panfrost/vulkan/panvk_vX_cmd_buffer.c b/src/panfrost/vulkan/panvk_vX_cmd_buffer.c index ff48cc0074c..4909a54435e 100644 --- a/src/panfrost/vulkan/panvk_vX_cmd_buffer.c +++ b/src/panfrost/vulkan/panvk_vX_cmd_buffer.c @@ -537,8 +537,13 @@ panvk_draw_prepare_fs_rsd(struct panvk_cmd_buffer *cmdbuf, return; } - if (!cmdbuf->state.gfx.fs_rsd) { + bool dirty = + is_dirty(cmdbuf, RS_DEPTH_BIAS_FACTORS) || !cmdbuf->state.gfx.fs_rsd; + + if (dirty) { const struct panvk_cmd_graphics_state *state = &cmdbuf->state.gfx; + const struct vk_rasterization_state *rs = + &cmdbuf->vk.dynamic_graphics_state.rs; struct panfrost_ptr rsd = pan_pool_alloc_desc_aggregate( &cmdbuf->desc_pool.base, PAN_DESC(RENDERER_STATE), PAN_DESC_ARRAY(pipeline->state.blend.pstate.rt_count, BLEND)); @@ -548,12 +553,9 @@ panvk_draw_prepare_fs_rsd(struct panvk_cmd_buffer *cmdbuf, &pipeline->state.fs.rsd_template; pan_pack(&rsd_dyn, RENDERER_STATE, cfg) { - if (pipeline->state.dynamic_mask & - (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) { - cfg.depth_units = state->rast.depth_bias.constant_factor * 2.0f; - cfg.depth_factor = state->rast.depth_bias.slope_factor; - cfg.depth_bias_clamp = state->rast.depth_bias.clamp; - } + cfg.depth_units = rs->depth_bias.constant * 2.0f; + cfg.depth_factor = rs->depth_bias.slope; + cfg.depth_bias_clamp = rs->depth_bias.clamp; if (pipeline->state.dynamic_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) { @@ -738,9 +740,7 @@ panvk_draw_prepare_varyings(struct panvk_cmd_buffer *cmdbuf, } else if (pipeline->state.ia.topology == MALI_DRAW_MODE_LINES || pipeline->state.ia.topology == MALI_DRAW_MODE_LINE_STRIP || pipeline->state.ia.topology == MALI_DRAW_MODE_LINE_LOOP) { - draw->line_width = pipeline->state.dynamic_mask & PANVK_DYNAMIC_LINE_WIDTH - ? cmdbuf->state.gfx.rast.line_width - : pipeline->state.rast.line_width; + draw->line_width = cmdbuf->vk.dynamic_graphics_state.rs.line.width; } else { draw->line_width = 1.0f; } @@ -1137,13 +1137,17 @@ panvk_emit_tiler_primitive_size(const struct panvk_graphics_pipeline *pipeline, } static void -panvk_emit_tiler_dcd(const struct panvk_graphics_pipeline *pipeline, +panvk_emit_tiler_dcd(struct panvk_cmd_buffer *cmdbuf, const struct panvk_draw_info *draw, void *dcd) { + const struct panvk_graphics_pipeline *pipeline = cmdbuf->state.gfx.pipeline; + const struct vk_rasterization_state *rs = + &cmdbuf->vk.dynamic_graphics_state.rs; + pan_pack(dcd, DRAW, cfg) { - cfg.front_face_ccw = pipeline->state.rast.front_ccw; - cfg.cull_front_face = pipeline->state.rast.cull_front_face; - cfg.cull_back_face = pipeline->state.rast.cull_back_face; + cfg.front_face_ccw = rs->front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE; + cfg.cull_front_face = (rs->cull_mode & VK_CULL_MODE_FRONT_BIT) != 0; + cfg.cull_back_face = (rs->cull_mode & VK_CULL_MODE_BACK_BIT) != 0; cfg.position = draw->position; cfg.state = draw->fs_rsd; cfg.attributes = draw->stages[MESA_SHADER_FRAGMENT].attributes; @@ -1200,7 +1204,7 @@ panvk_draw_prepare_tiler_job(struct panvk_cmd_buffer *cmdbuf, panvk_emit_tiler_primitive_size( pipeline, draw, pan_section_ptr(ptr.cpu, TILER_JOB, PRIMITIVE_SIZE)); - panvk_emit_tiler_dcd(pipeline, draw, + panvk_emit_tiler_dcd(cmdbuf, draw, pan_section_ptr(ptr.cpu, TILER_JOB, DRAW)); pan_section_pack(ptr.cpu, TILER_JOB, TILER, cfg) { @@ -1254,6 +1258,8 @@ panvk_cmd_draw(struct panvk_cmd_buffer *cmdbuf, struct panvk_draw_info *draw) struct panvk_batch *batch = cmdbuf->cur_batch; struct panvk_descriptor_state *desc_state = &cmdbuf->state.gfx.desc_state; const struct panvk_graphics_pipeline *pipeline = cmdbuf->state.gfx.pipeline; + const struct vk_rasterization_state *rs = + &cmdbuf->vk.dynamic_graphics_state.rs; /* There are only 16 bits in the descriptor for the job ID, make sure all * the 3 (2 in Bifrost) jobs in this draw are in the same batch. @@ -1264,7 +1270,7 @@ panvk_cmd_draw(struct panvk_cmd_buffer *cmdbuf, struct panvk_draw_info *draw) batch = panvk_per_arch(cmd_open_batch)(cmdbuf); } - if (pipeline->state.rast.enable) + if (!rs->rasterizer_discard_enable) panvk_per_arch(cmd_alloc_fb_desc)(cmdbuf); panvk_per_arch(cmd_alloc_tls_desc)(cmdbuf, true); @@ -1304,7 +1310,7 @@ panvk_cmd_draw(struct panvk_cmd_buffer *cmdbuf, struct panvk_draw_info *draw) pan_jc_add_job(&cmdbuf->desc_pool.base, &batch->jc, MALI_JOB_TYPE_VERTEX, false, false, 0, 0, &draw->jobs.vertex, false); - if (pipeline->state.rast.enable && draw->position) { + if (!rs->rasterizer_discard_enable && draw->position) { pan_jc_add_job(&cmdbuf->desc_pool.base, &batch->jc, MALI_JOB_TYPE_TILER, false, false, vjob_id, 0, &draw->jobs.tiler, false); } @@ -2145,30 +2151,6 @@ panvk_per_arch(CmdBindPipeline)(VkCommandBuffer commandBuffer, } } -VKAPI_ATTR void VKAPI_CALL -panvk_per_arch(CmdSetLineWidth)(VkCommandBuffer commandBuffer, float lineWidth) -{ - VK_FROM_HANDLE(panvk_cmd_buffer, cmdbuf, commandBuffer); - - cmdbuf->state.gfx.rast.line_width = lineWidth; - cmdbuf->state.gfx.dirty |= PANVK_DYNAMIC_LINE_WIDTH; -} - -VKAPI_ATTR void VKAPI_CALL -panvk_per_arch(CmdSetDepthBias)(VkCommandBuffer commandBuffer, - float depthBiasConstantFactor, - float depthBiasClamp, - float depthBiasSlopeFactor) -{ - VK_FROM_HANDLE(panvk_cmd_buffer, cmdbuf, commandBuffer); - - cmdbuf->state.gfx.rast.depth_bias.constant_factor = depthBiasConstantFactor; - cmdbuf->state.gfx.rast.depth_bias.clamp = depthBiasClamp; - cmdbuf->state.gfx.rast.depth_bias.slope_factor = depthBiasSlopeFactor; - cmdbuf->state.gfx.dirty |= PANVK_DYNAMIC_DEPTH_BIAS; - cmdbuf->state.gfx.fs_rsd = 0; -} - VKAPI_ATTR void VKAPI_CALL panvk_per_arch(CmdSetBlendConstants)(VkCommandBuffer commandBuffer, const float blendConstants[4]) diff --git a/src/panfrost/vulkan/panvk_vX_pipeline.c b/src/panfrost/vulkan/panvk_vX_pipeline.c index 7032e942230..f2654f611d5 100644 --- a/src/panfrost/vulkan/panvk_vX_pipeline.c +++ b/src/panfrost/vulkan/panvk_vX_pipeline.c @@ -142,9 +142,11 @@ emit_non_fs_rsd(const struct pan_shader_info *shader_info, mali_ptr shader_ptr, } static void -emit_base_fs_rsd(const struct panvk_graphics_pipeline *pipeline, void *rsd) +emit_base_fs_rsd(const struct panvk_graphics_pipeline *pipeline, + const struct vk_graphics_pipeline_state *state, void *rsd) { const struct pan_shader_info *info = &pipeline->state.fs.info; + const struct vk_rasterization_state *rs = state->rs; pan_pack(rsd, RENDERER_STATE, cfg) { if (pipeline->state.fs.required) { @@ -188,27 +190,23 @@ emit_base_fs_rsd(const struct panvk_graphics_pipeline *pipeline, void *rsd) cfg.multisample_misc.depth_write_mask = pipeline->state.zs.z_write; cfg.multisample_misc.fixed_function_near_discard = - !pipeline->state.rast.clamp_depth; - cfg.multisample_misc.fixed_function_far_discard = - !pipeline->state.rast.clamp_depth; + !rs->depth_clamp_enable; + cfg.multisample_misc.fixed_function_far_discard = !rs->depth_clamp_enable; cfg.multisample_misc.shader_depth_range_fixed = true; cfg.stencil_mask_misc.stencil_enable = pipeline->state.zs.s_test; cfg.stencil_mask_misc.alpha_to_coverage = pipeline->state.ms.alpha_to_coverage; cfg.stencil_mask_misc.alpha_test_compare_function = MALI_FUNC_ALWAYS; - cfg.stencil_mask_misc.front_facing_depth_bias = - pipeline->state.rast.depth_bias.enable; - cfg.stencil_mask_misc.back_facing_depth_bias = - pipeline->state.rast.depth_bias.enable; + cfg.stencil_mask_misc.front_facing_depth_bias = rs->depth_bias.enable; + cfg.stencil_mask_misc.back_facing_depth_bias = rs->depth_bias.enable; cfg.stencil_mask_misc.single_sampled_lines = pipeline->state.ms.rast_samples <= 1; if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS)) { - cfg.depth_units = - pipeline->state.rast.depth_bias.constant_factor * 2.0f; - cfg.depth_factor = pipeline->state.rast.depth_bias.slope_factor; - cfg.depth_bias_clamp = pipeline->state.rast.depth_bias.clamp; + cfg.depth_units = rs->depth_bias.constant * 2.0f; + cfg.depth_factor = rs->depth_bias.slope; + cfg.depth_bias_clamp = rs->depth_bias.clamp; } if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK)) { @@ -325,6 +323,7 @@ emit_blend(const struct panvk_graphics_pipeline *pipeline, unsigned rt, static void init_shaders(struct panvk_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *gfx_create_info, + const struct vk_graphics_pipeline_state *gfx_state, struct panvk_shader **shaders) { struct panvk_graphics_pipeline *gfx_pipeline = @@ -379,7 +378,7 @@ init_shaders(struct panvk_pipeline *pipeline, PAN_DESC_ARRAY(bd_count, BLEND)); void *bd = rsd.cpu + pan_size(RENDERER_STATE); - emit_base_fs_rsd(gfx_pipeline, rsd.cpu); + emit_base_fs_rsd(gfx_pipeline, gfx_state, rsd.cpu); for (unsigned rt = 0; rt < gfx_pipeline->state.blend.pstate.rt_count; rt++) { emit_blend(gfx_pipeline, rt, bd); @@ -388,7 +387,7 @@ init_shaders(struct panvk_pipeline *pipeline, pipeline->rsds[MESA_SHADER_FRAGMENT] = rsd.gpu; } else if (gfx_create_info) { - emit_base_fs_rsd(gfx_pipeline, + emit_base_fs_rsd(gfx_pipeline, gfx_state, gfx_pipeline->state.fs.rsd_template.opaque); for (unsigned rt = 0; rt < MAX2(gfx_pipeline->state.blend.pstate.rt_count, 1); rt++) { @@ -405,10 +404,6 @@ static void parse_dynamic_state(struct panvk_graphics_pipeline *pipeline, const struct vk_graphics_pipeline_state *state) { - if (is_dyn(state, RS_LINE_WIDTH)) - pipeline->state.dynamic_mask |= PANVK_DYNAMIC_LINE_WIDTH; - if (is_dyn(state, RS_DEPTH_BIAS_FACTORS)) - pipeline->state.dynamic_mask |= PANVK_DYNAMIC_DEPTH_BIAS; if (is_dyn(state, CB_BLEND_CONSTANTS)) pipeline->state.dynamic_mask |= PANVK_DYNAMIC_BLEND_CONSTANTS; if (is_dyn(state, DS_DEPTH_BOUNDS_TEST_BOUNDS)) @@ -659,26 +654,6 @@ parse_zs(struct panvk_graphics_pipeline *pipeline, pipeline->state.zs.s_back.ref = ds->stencil.back.reference; } -static void -parse_rast(struct panvk_graphics_pipeline *pipeline, - const struct vk_graphics_pipeline_state *state) -{ - const struct vk_rasterization_state *rs = state->rs; - - pipeline->state.rast.clamp_depth = rs->depth_clamp_enable; - pipeline->state.rast.depth_bias.enable = rs->depth_bias.enable; - pipeline->state.rast.depth_bias.constant_factor = rs->depth_bias.constant; - pipeline->state.rast.depth_bias.clamp = rs->depth_bias.clamp; - pipeline->state.rast.depth_bias.slope_factor = rs->depth_bias.slope; - pipeline->state.rast.front_ccw = - rs->front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE; - pipeline->state.rast.cull_front_face = - rs->cull_mode & VK_CULL_MODE_FRONT_BIT; - pipeline->state.rast.cull_back_face = rs->cull_mode & VK_CULL_MODE_BACK_BIT; - pipeline->state.rast.line_width = rs->line.width; - pipeline->state.rast.enable = !rs->rasterizer_discard_enable; -} - static bool fs_required(struct panvk_graphics_pipeline *pipeline) { @@ -882,10 +857,9 @@ panvk_graphics_pipeline_create(struct panvk_device *dev, parse_input_assembly(gfx_pipeline, &state); parse_multisample(gfx_pipeline, &state); parse_zs(gfx_pipeline, &state); - parse_rast(gfx_pipeline, &state); parse_vertex_input(gfx_pipeline, &state, shaders); init_fs_state(gfx_pipeline, &state, shaders[MESA_SHADER_FRAGMENT]); - init_shaders(&gfx_pipeline->base, create_info, shaders); + init_shaders(&gfx_pipeline->base, create_info, &state, shaders); release_shaders(&gfx_pipeline->base, shaders, alloc); return VK_SUCCESS; @@ -948,7 +922,7 @@ panvk_compute_pipeline_create(struct panvk_device *dev, compile_shaders(&compute_pipeline->base, &create_info->stage, 1, alloc, shaders); - init_shaders(&compute_pipeline->base, NULL, shaders); + init_shaders(&compute_pipeline->base, NULL, NULL, shaders); release_shaders(&compute_pipeline->base, shaders, alloc); return VK_SUCCESS;