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tu: Move RENDER_COMPONENTS setting to pipeline state

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This needs to be pipeline state because it can change when dual-source
blending is active.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5039>
This commit is contained in:
Connor Abbott
2020-05-14 16:41:02 +02:00
committed by Marge Bot
parent 2a9d12d513
commit 078aa9df8d
4 changed files with 8 additions and 10 deletions
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5
src/freedreno/vulkan/tu_cmd_buffer.c
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@@ -448,11 +448,6 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs,
A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
tu_cs_emit_regs(cs,
A6XX_RB_RENDER_COMPONENTS(.dword = subpass->render_components));
tu_cs_emit_regs(cs,
A6XX_SP_FS_RENDER_COMPONENTS(.dword = subpass->render_components));
tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(fb->layers - 1));
}

3
src/freedreno/vulkan/tu_pass.c
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@@ -100,15 +100,12 @@ create_render_pass_common(struct tu_render_pass *pass,
struct tu_subpass *subpass = &pass->subpasses[i];
subpass->srgb_cntl = 0;
subpass->render_components = 0;
for (uint32_t i = 0; i < subpass->color_count; ++i) {
uint32_t a = subpass->color_attachments[i].attachment;
if (a == VK_ATTACHMENT_UNUSED)
continue;
subpass->render_components |= 0xf << (i * 4);
if (vk_format_is_srgb(pass->attachments[a].format))
subpass->srgb_cntl |= 1 << i;
}

8
src/freedreno/vulkan/tu_pipeline.c
View File

@@ -1322,6 +1322,8 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
}
uint32_t render_components = (1 << (4 * mrt_count)) - 1;
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
@@ -1336,11 +1338,17 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
(false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
}
tu_cs_emit_regs(cs,
A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
tu_cs_emit_regs(cs,
A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
uint32_t gras_su_depth_plane_cntl = 0;
uint32_t rb_depth_plane_cntl = 0;
if (fs->no_earlyz || fs->writes_pos) {

2
src/freedreno/vulkan/tu_private.h
View File

@@ -1612,8 +1612,6 @@ struct tu_subpass
VkSampleCountFlagBits samples;
/* pre-filled register values */
uint32_t render_components;
uint32_t srgb_cntl;
};