OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

iris: store workaround address

Browse Source 
This will allow to select a different address later, leaving the
beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
This commit is contained in:
Lionel Landwerlin
2020-02-21 18:06:18 +02:00
committed by Marge Bot
parent 33b452aae7
commit 07781f0afe
6 changed files with 23 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/gallium/drivers/iris/iris_batch.h
View File

@@ -57,12 +57,6 @@ enum iris_batch_name {
#define IRIS_BATCH_COUNT 2
struct iris_address {
struct iris_bo *bo;
uint64_t offset;
bool write;
};
struct iris_batch {
struct iris_screen *screen;
struct pipe_debug_callback *dbg;

5
src/gallium/drivers/iris/iris_blorp.c
View File

@@ -228,7 +228,10 @@ blorp_get_workaround_address(struct blorp_batch *blorp_batch)
{
struct iris_batch *batch = blorp_batch->driver_batch;
return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
return (struct blorp_address) {
.buffer = batch->screen->workaround_address.bo,
.offset = batch->screen->workaround_address.offset,
};
}
static void

3
src/gallium/drivers/iris/iris_pipe_control.c
View File

@@ -148,7 +148,8 @@ iris_emit_end_of_pipe_sync(struct iris_batch *batch,
iris_emit_pipe_control_write(batch, reason,
flags | PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_WRITE_IMMEDIATE,
batch->screen->workaround_bo, 0, 0);
batch->screen->workaround_address.bo,
batch->screen->workaround_address.offset, 0);
}
/**

5
src/gallium/drivers/iris/iris_screen.c
View File

@@ -718,6 +718,11 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
if (!screen->workaround_bo)
return NULL;
screen->workaround_address = (struct iris_address) {
.bo = screen->workaround_bo,
.offset = 0,
};
brw_process_intel_debug_variable();
screen->driconf.dual_color_blend_by_location =

7
src/gallium/drivers/iris/iris_screen.h
View File

@@ -136,6 +136,12 @@ struct iris_vtable {
void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
};
struct iris_address {
struct iris_bo *bo;
uint64_t offset;
bool write;
};
struct iris_screen {
struct pipe_screen base;
@@ -190,6 +196,7 @@ struct iris_screen {
* require scratch writes or reads from some unimportant memory.
*/
struct iris_bo *workaround_bo;
struct iris_address workaround_address;
struct disk_cache *disk_cache;
};

8
src/gallium/drivers/iris/iris_state.c
View File

@@ -5224,7 +5224,7 @@ setup_constant_buffers(struct iris_context *ice,
push_bos->buffers[n].length = range->length;
push_bos->buffers[n].addr =
res ? ro_bo(res->bo, range->start * 32 + cbuf->buffer_offset)
: ro_bo(batch->screen->workaround_bo, 0);
: batch->screen->workaround_address;
n++;
}
@@ -5971,7 +5971,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
*/
iris_emit_pipe_control_write(batch, "WA for stencil state",
PIPE_CONTROL_WRITE_IMMEDIATE,
batch->screen->workaround_bo, 0, 0);
batch->screen->workaround_address.bo,
batch->screen->workaround_address.offset, 0);
}
union isl_color_value clear_value = { .f32 = { 0, } };
@@ -6989,7 +6990,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
post_sync_flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
non_lri_post_sync_flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
bo = batch->screen->workaround_bo;
bo = batch->screen->workaround_address.bo;
offset = batch->screen->workaround_address.offset;
}
}