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intel/mi_builder: Support gen11 command-streamer based register offsets

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Reworks:
 * Automatically apply to any register in the range 0x2000 - 0x4000

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5466>
This commit is contained in:
Jordan Justen
2019-04-14 03:11:25 -07:00
parent fdb1997ab5
commit 06cf838cbd
1 changed files with 61 additions and 8 deletions
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69
src/intel/common/gen_mi_builder.h
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@@ -100,6 +100,27 @@ struct gen_mi_value {
#endif #endif
}; };
struct gen_mi_reg_num {
uint32_t num;
#if GEN_GEN >= 11
bool cs;
#endif
};
static inline struct gen_mi_reg_num
gen_mi_adjust_reg_num(uint32_t reg)
{
#if GEN_GEN >= 11
bool cs = reg >= 0x2000 && reg < 0x4000;
return (struct gen_mi_reg_num) {
.num = reg - (cs ? 0x2000 : 0),
.cs = cs,
};
#else
return (struct gen_mi_reg_num) { .num = reg, };
#endif
}
#if GEN_GEN >= 9 #if GEN_GEN >= 9
#define GEN_MI_BUILDER_MAX_MATH_DWORDS 256 #define GEN_MI_BUILDER_MAX_MATH_DWORDS 256
#else #else
@@ -400,7 +421,11 @@ _gen_mi_copy_no_unref(struct gen_mi_builder *b,
case GEN_MI_VALUE_TYPE_REG32: case GEN_MI_VALUE_TYPE_REG32:
case GEN_MI_VALUE_TYPE_REG64: case GEN_MI_VALUE_TYPE_REG64:
gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) {
srm.RegisterAddress = src.reg; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(src.reg);
srm.RegisterAddress = reg.num;
#if GEN_GEN >= 11
srm.AddCSMMIOStartOffset = reg.cs;
#endif
srm.MemoryAddress = dst.addr; srm.MemoryAddress = dst.addr;
} }
break; break;
@@ -414,7 +439,11 @@ _gen_mi_copy_no_unref(struct gen_mi_builder *b,
switch (src.type) { switch (src.type) {
case GEN_MI_VALUE_TYPE_IMM: case GEN_MI_VALUE_TYPE_IMM:
gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) { gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = dst.reg; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(dst.reg);
lri.RegisterOffset = reg.num;
#if GEN_GEN >= 11
lri.AddCSMMIOStartOffset = reg.cs;
#endif
lri.DataDWord = src.imm; lri.DataDWord = src.imm;
} }
break; break;
@@ -422,7 +451,11 @@ _gen_mi_copy_no_unref(struct gen_mi_builder *b,
case GEN_MI_VALUE_TYPE_MEM32: case GEN_MI_VALUE_TYPE_MEM32:
case GEN_MI_VALUE_TYPE_MEM64: case GEN_MI_VALUE_TYPE_MEM64:
gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_MEM), lrm) { gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = dst.reg; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(dst.reg);
lrm.RegisterAddress = reg.num;
#if GEN_GEN >= 11
lrm.AddCSMMIOStartOffset = reg.cs;
#endif
lrm.MemoryAddress = src.addr; lrm.MemoryAddress = src.addr;
} }
break; break;
@@ -432,8 +465,16 @@ _gen_mi_copy_no_unref(struct gen_mi_builder *b,
#if GEN_GEN >= 8 || GEN_IS_HASWELL #if GEN_GEN >= 8 || GEN_IS_HASWELL
if (src.reg != dst.reg) { if (src.reg != dst.reg) {
gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) { gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) {
lrr.SourceRegisterAddress = src.reg; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(src.reg);
lrr.DestinationRegisterAddress = dst.reg; lrr.SourceRegisterAddress = reg.num;
#if GEN_GEN >= 11
lrr.AddCSMMIOStartOffsetSource = reg.cs;
#endif
reg = gen_mi_adjust_reg_num(dst.reg);
lrr.DestinationRegisterAddress = reg.num;
#if GEN_GEN >= 11
lrr.AddCSMMIOStartOffsetDestination = reg.cs;
#endif
} }
} }
#else #else
@@ -551,18 +592,30 @@ gen_mi_store_if(struct gen_mi_builder *b,
if (dst.type == GEN_MI_VALUE_TYPE_MEM64) { if (dst.type == GEN_MI_VALUE_TYPE_MEM64) {
gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) {
srm.RegisterAddress = src.reg; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(src.reg);
srm.RegisterAddress = reg.num;
#if GEN_GEN >= 11
srm.AddCSMMIOStartOffset = reg.cs;
#endif
srm.MemoryAddress = dst.addr; srm.MemoryAddress = dst.addr;
srm.PredicateEnable = true; srm.PredicateEnable = true;
} }
gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) {
srm.RegisterAddress = src.reg + 4; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(src.reg + 4);
srm.RegisterAddress = reg.num;
#if GEN_GEN >= 11
srm.AddCSMMIOStartOffset = reg.cs;
#endif
srm.MemoryAddress = __gen_address_offset(dst.addr, 4); srm.MemoryAddress = __gen_address_offset(dst.addr, 4);
srm.PredicateEnable = true; srm.PredicateEnable = true;
} }
} else { } else {
gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) {
srm.RegisterAddress = src.reg; struct gen_mi_reg_num reg = gen_mi_adjust_reg_num(src.reg);
srm.RegisterAddress = reg.num;
#if GEN_GEN >= 11
srm.AddCSMMIOStartOffset = reg.cs;
#endif
srm.MemoryAddress = dst.addr; srm.MemoryAddress = dst.addr;
srm.PredicateEnable = true; srm.PredicateEnable = true;
} }