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intel/fs: enable SSBO accesses through the bindless heap

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Using the information coming from surface_index_intel, we can tell
whether we should use the BTI or bindless heap for a particular SSBO
access.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21645>
This commit is contained in:
Lionel Landwerlin
2022-12-21 13:30:40 +02:00
committed by Marge Bot
parent 3d0cc3f63b
commit 068bf1378d
3 changed files with 30 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/compiler/brw_fs.h
View File

@@ -363,7 +363,7 @@ public:
nir_intrinsic_instr *instr); nir_intrinsic_instr *instr);
fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld, fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
nir_intrinsic_instr *instr); nir_intrinsic_instr *instr);
fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld, fs_reg get_nir_buffer_intrinsic_index(const brw::fs_builder &bld,
nir_intrinsic_instr *instr); nir_intrinsic_instr *instr);
fs_reg swizzle_nir_scratch_addr(const brw::fs_builder &bld, fs_reg swizzle_nir_scratch_addr(const brw::fs_builder &bld,
const fs_reg &addr, const fs_reg &addr,

29
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -3954,7 +3954,7 @@ fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder &bld,
} }
fs_reg fs_reg
fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld, fs_visitor::get_nir_buffer_intrinsic_index(const brw::fs_builder &bld,
nir_intrinsic_instr *instr) nir_intrinsic_instr *instr)
{ {
/* SSBO stores are weird in that their index is in src[1] */ /* SSBO stores are weird in that their index is in src[1] */
@@ -4886,8 +4886,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
const unsigned bit_size = nir_dest_bit_size(instr->dest); const unsigned bit_size = nir_dest_bit_size(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = srcs[get_nir_src_bindless(instr->src[0]) ?
get_nir_ssbo_intrinsic_index(bld, instr); SURFACE_LOGICAL_SRC_SURFACE_HANDLE :
SURFACE_LOGICAL_SRC_SURFACE] =
get_nir_buffer_intrinsic_index(bld, instr);
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0); srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0);
@@ -4923,8 +4925,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
const unsigned bit_size = nir_src_bit_size(instr->src[0]); const unsigned bit_size = nir_src_bit_size(instr->src[0]);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = srcs[get_nir_src_bindless(instr->src[1]) ?
get_nir_ssbo_intrinsic_index(bld, instr); SURFACE_LOGICAL_SRC_SURFACE_HANDLE :
SURFACE_LOGICAL_SRC_SURFACE] =
get_nir_buffer_intrinsic_index(bld, instr);
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[2]); srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[2]);
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1);
@@ -4963,7 +4967,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
const bool is_ssbo = const bool is_ssbo =
instr->intrinsic == nir_intrinsic_load_ssbo_uniform_block_intel; instr->intrinsic == nir_intrinsic_load_ssbo_uniform_block_intel;
srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ? srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ?
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GFX7_BTI_SLM)); get_nir_buffer_intrinsic_index(bld, instr) :
fs_reg(brw_imm_ud(GFX7_BTI_SLM));
const unsigned total_dwords = ALIGN(instr->num_components, REG_SIZE / 4); const unsigned total_dwords = ALIGN(instr->num_components, REG_SIZE / 4);
unsigned loaded_dwords = 0; unsigned loaded_dwords = 0;
@@ -5032,7 +5037,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_ssbo_atomic: case nir_intrinsic_ssbo_atomic:
case nir_intrinsic_ssbo_atomic_swap: case nir_intrinsic_ssbo_atomic_swap:
nir_emit_surface_atomic(bld, instr, nir_emit_surface_atomic(bld, instr,
get_nir_ssbo_intrinsic_index(bld, instr)); get_nir_buffer_intrinsic_index(bld, instr));
break; break;
case nir_intrinsic_get_ssbo_size: { case nir_intrinsic_get_ssbo_size: {
@@ -5697,7 +5702,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ? srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ?
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GFX7_BTI_SLM)); get_nir_buffer_intrinsic_index(bld, instr) :
fs_reg(brw_imm_ud(GFX7_BTI_SLM));
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address; srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address;
const fs_builder ubld1 = bld.exec_all().group(1, 0); const fs_builder ubld1 = bld.exec_all().group(1, 0);
@@ -5739,7 +5745,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ? srcs[SURFACE_LOGICAL_SRC_SURFACE] = is_ssbo ?
get_nir_ssbo_intrinsic_index(bld, instr) : fs_reg(brw_imm_ud(GFX7_BTI_SLM)); get_nir_buffer_intrinsic_index(bld, instr) :
fs_reg(brw_imm_ud(GFX7_BTI_SLM));
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address; srcs[SURFACE_LOGICAL_SRC_ADDRESS] = address;
const fs_builder ubld1 = bld.exec_all().group(1, 0); const fs_builder ubld1 = bld.exec_all().group(1, 0);
@@ -5967,7 +5974,9 @@ fs_visitor::nir_emit_surface_atomic(const fs_builder &bld,
fs_reg dest = get_nir_dest(instr->dest); fs_reg dest = get_nir_dest(instr->dest);
fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
srcs[SURFACE_LOGICAL_SRC_SURFACE] = surface; srcs[get_nir_src_bindless(instr->src[0]) ?
SURFACE_LOGICAL_SRC_SURFACE_HANDLE :
SURFACE_LOGICAL_SRC_SURFACE] = surface;
srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op); srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1); srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1);

8
src/intel/compiler/brw_lower_logical_sends.cpp
View File

@@ -1727,8 +1727,14 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
enum lsc_addr_surface_type surf_type; enum lsc_addr_surface_type surf_type;
if (surface_handle.file != BAD_FILE) { if (surface_handle.file != BAD_FILE) {
assert(surface.file == IMM && (surface.ud == 0 || surface.ud == GFX125_NON_BINDLESS)); if (surface.file == BAD_FILE) {
assert(!non_bindless);
surf_type = LSC_ADDR_SURFTYPE_BSS;
} else {
assert(surface.file == IMM &&
(surface.ud == 0 || surface.ud == GFX125_NON_BINDLESS));
surf_type = non_bindless ? LSC_ADDR_SURFTYPE_SS : LSC_ADDR_SURFTYPE_BSS; surf_type = non_bindless ? LSC_ADDR_SURFTYPE_SS : LSC_ADDR_SURFTYPE_BSS;
}
} else if (surface.file == IMM && surface.ud == GFX7_BTI_SLM) } else if (surface.file == IMM && surface.ud == GFX7_BTI_SLM)
surf_type = LSC_ADDR_SURFTYPE_FLAT; surf_type = LSC_ADDR_SURFTYPE_FLAT;
else else