freedreno/ir3: Skip DAG validation on release builds

Was triggering a stack overflow in android CTS with
dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.lots_ids and
friends, presumably due to smaller stack size with bionic.  But there
isn't really any point to doing this validation in release builds so
lets limit it to debug builds (which will cover mesa-CI).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29088>

src/freedreno/ir3/ir3_postsched.c

@@ -104,6 +104,7 @@ has_ss_src(struct ir3_instruction *instr)
    return node->has_ss_src;
 }
 
+#ifndef NDEBUG
 static void
 sched_dag_validate_cb(const struct dag_node *node, void *data)
 {
@@ -111,6 +112,7 @@ sched_dag_validate_cb(const struct dag_node *node, void *data)
 
    ir3_print_instr(n->instr);
 }
+#endif
 
 static void
 schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
@@ -642,7 +644,9 @@ sched_dag_init(struct ir3_postsched_ctx *ctx)
       }
    }
 
+#ifndef NDEBUG
    dag_validate(ctx->dag, sched_dag_validate_cb, NULL);
+#endif
 
    // TODO do we want to do this after reverse-dependencies?
    dag_traverse_bottom_up(ctx->dag, sched_dag_max_delay_cb, NULL);

src/freedreno/ir3/ir3_sched.c

@@ -1085,6 +1085,7 @@ sched_dag_max_delay_cb(struct dag_node *node, void *state)
    n->max_delay = MAX2(n->max_delay, max_delay + n->delay);
 }
 
+#ifndef NDEBUG
 static void
 sched_dag_validate_cb(const struct dag_node *node, void *data)
 {
@@ -1092,6 +1093,7 @@ sched_dag_validate_cb(const struct dag_node *node, void *data)
 
    ir3_print_instr(n->instr);
 }
+#endif
 
 static void
 sched_dag_init(struct ir3_sched_ctx *ctx)
@@ -1101,7 +1103,9 @@ sched_dag_init(struct ir3_sched_ctx *ctx)
    foreach_instr (instr, &ctx->unscheduled_list)
       sched_node_init(ctx, instr);
 
+#ifndef NDEBUG
    dag_validate(ctx->dag, sched_dag_validate_cb, NULL);
+#endif
 
    foreach_instr (instr, &ctx->unscheduled_list)
       sched_node_add_deps(ctx, instr);