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intel: Add intel_gem_create_context_engines

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Engines based contexts operate somewhat different for executing
batches. Previously, we would specify a bitmask value such as
I915_EXEC_RENDER to specify to run the batch on the render ring.

With engines contexts, instead this becomes an array of "engines", and
when the context is created we specify the class and instance of the
engine.

Each index in the array has a separate hardware-context. Previously we
had to create separate kernel level contexts to create multiple
hardware contexts, but now a single kernel context can own multiple
hardware contexts.

Another forward looking advantage to using the engines based contexts
is that the kernel does not plan to add new supported I915_EXEC_FOO
masks, whereas they instead plan to add new I915_ENGINE_CLASS_FOO
engine classes. Therefore some rings may only be usable with an engine
based class.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12692>
This commit is contained in:
Jordan Justen
2021-08-31 02:29:41 -07:00
parent 9a9042a904
commit 0634cb741b
6 changed files with 92 additions and 100 deletions
Download Patch File Download Diff File Expand all files Collapse all files

86
src/intel/common/intel_gem.c
View File

@@ -68,3 +68,89 @@ intel_gem_count_engines(const struct drm_i915_query_engine_info *info,
}
return count;
}
int
intel_gem_create_context_engines(int fd,
const struct drm_i915_query_engine_info *info,
int num_engines, uint16_t *engine_classes)
{
assert(info != NULL);
const size_t engine_inst_sz = 2 * sizeof(__u16); /* 1 class, 1 instance */
const size_t engines_param_size =
sizeof(__u64) /* extensions */ + num_engines * engine_inst_sz;
void *engines_param = malloc(engines_param_size);
assert(engines_param);
*(__u64*)engines_param = 0;
__u16 *class_inst_ptr = (__u16*)(((__u64*)engines_param) + 1);
/* For each type of drm_i915_gem_engine_class of interest, we keep track of
* the previous engine instance used.
*/
int last_engine_idx[] = {
[I915_ENGINE_CLASS_RENDER] = -1,
};
int i915_engine_counts[] = {
[I915_ENGINE_CLASS_RENDER] =
intel_gem_count_engines(info, I915_ENGINE_CLASS_RENDER),
};
/* For each queue, we look for the next instance that matches the class we
* need.
*/
for (int i = 0; i < num_engines; i++) {
uint16_t engine_class = engine_classes[i];
assert(engine_class == I915_ENGINE_CLASS_RENDER);
if (i915_engine_counts[engine_class] <= 0) {
free(engines_param);
return -1;
}
/* Run through the engines reported by the kernel looking for the next
* matching instance. We loop in case we want to create multiple
* contexts on an engine instance.
*/
int engine_instance = -1;
for (int i = 0; i < info->num_engines; i++) {
int *idx = &last_engine_idx[engine_class];
if (++(*idx) >= info->num_engines)
*idx = 0;
if (info->engines[*idx].engine.engine_class == engine_class) {
engine_instance = info->engines[*idx].engine.engine_instance;
break;
}
}
if (engine_instance < 0) {
free(engines_param);
return -1;
}
*class_inst_ptr++ = engine_class;
*class_inst_ptr++ = engine_instance;
}
assert((uintptr_t)engines_param + engines_param_size ==
(uintptr_t)class_inst_ptr);
struct drm_i915_gem_context_create_ext_setparam set_engines = {
.base = {
.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
},
.param = {
.param = I915_CONTEXT_PARAM_ENGINES,
.value = (uintptr_t)engines_param,
.size = engines_param_size,
}
};
struct drm_i915_gem_context_create_ext create = {
.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
.extensions = (uintptr_t)&set_engines,
};
int ret = intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create);
free(engines_param);
if (ret == -1)
return -1;
return create.ctx_id;
}

3
src/intel/common/intel_gem.h
View File

@@ -148,5 +148,8 @@ bool intel_gem_supports_syncobj_wait(int fd);
int intel_gem_count_engines(const struct drm_i915_query_engine_info *info,
enum drm_i915_gem_engine_class engine_class);
int intel_gem_create_context_engines(int fd,
const struct drm_i915_query_engine_info *info,
int num_engines, uint16_t *engine_classes);
#endif /* INTEL_GEM_H */

2
src/intel/vulkan/anv_device.c
View File

@@ -3063,7 +3063,7 @@ VkResult anv_CreateDevice(
engine_classes[engine_count++] = queue_family->engine_class;
}
device->context_id =
anv_gem_create_context_engines(device,
intel_gem_create_context_engines(device->fd,
physical_device->engine_info,
engine_count, engine_classes);
} else {

84
src/intel/vulkan/anv_gem.c
View File

@@ -337,90 +337,6 @@ anv_gem_create_context(struct anv_device *device)
return create.ctx_id;
}
int
anv_gem_create_context_engines(struct anv_device *device,
const struct drm_i915_query_engine_info *info,
int num_engines, uint16_t *engine_classes)
{
const size_t engine_inst_sz = 2 * sizeof(__u16); /* 1 class, 1 instance */
const size_t engines_param_size =
sizeof(__u64) /* extensions */ + num_engines * engine_inst_sz;
void *engines_param = malloc(engines_param_size);
assert(engines_param);
*(__u64*)engines_param = 0;
__u16 *class_inst_ptr = (__u16*)(((__u64*)engines_param) + 1);
/* For each type of drm_i915_gem_engine_class of interest, we keep track of
* the previous engine instance used.
*/
int last_engine_idx[] = {
[I915_ENGINE_CLASS_RENDER] = -1,
};
int i915_engine_counts[] = {
[I915_ENGINE_CLASS_RENDER] =
intel_gem_count_engines(info, I915_ENGINE_CLASS_RENDER),
};
/* For each queue, we look for the next instance that matches the class we
* need.
*/
for (int i = 0; i < num_engines; i++) {
uint16_t engine_class = engine_classes[i];
if (i915_engine_counts[engine_class] <= 0) {
free(engines_param);
return -1;
}
/* Run through the engines reported by the kernel looking for the next
* matching instance. We loop in case we want to create multiple
* contexts on an engine instance.
*/
int engine_instance = -1;
for (int i = 0; i < info->num_engines; i++) {
int *idx = &last_engine_idx[engine_class];
if (++(*idx) >= info->num_engines)
*idx = 0;
if (info->engines[*idx].engine.engine_class == engine_class) {
engine_instance = info->engines[*idx].engine.engine_instance;
break;
}
}
if (engine_instance < 0) {
free(engines_param);
return -1;
}
*class_inst_ptr++ = engine_class;
*class_inst_ptr++ = engine_instance;
}
assert((uintptr_t)engines_param + engines_param_size ==
(uintptr_t)class_inst_ptr);
struct drm_i915_gem_context_create_ext_setparam set_engines = {
.base = {
.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
},
.param = {
.param = I915_CONTEXT_PARAM_ENGINES,
.value = (uintptr_t)engines_param,
.size = engines_param_size,
}
};
struct drm_i915_gem_context_create_ext create = {
.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
.extensions = (uintptr_t)&set_engines,
};
int ret = intel_ioctl(device->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create);
free(engines_param);
if (ret == -1)
return -1;
return create.ctx_id;
}
int
anv_gem_destroy_context(struct anv_device *device, int context)
{

9
src/intel/vulkan/anv_gem_stubs.c
View File

@@ -193,15 +193,6 @@ anv_i915_query(int fd, uint64_t query_id, void *buffer,
unreachable("Unused");
}
int
anv_gem_create_context_engines(struct anv_device *device,
const struct drm_i915_query_engine_info *info,
int num_engines,
uint16_t *engine_classes)
{
unreachable("Unused");
}
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{

4
src/intel/vulkan/anv_private.h
View File

@@ -1365,10 +1365,6 @@ int anv_gem_execbuffer(struct anv_device *device,
int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
uint32_t stride, uint32_t tiling);
int anv_gem_create_context(struct anv_device *device);
int anv_gem_create_context_engines(struct anv_device *device,
const struct drm_i915_query_engine_info *info,
int num_engines,
uint16_t *engine_classes);
bool anv_gem_has_context_priority(int fd, int priority);
int anv_gem_destroy_context(struct anv_device *device, int context);
int anv_gem_set_context_param(int fd, int context, uint32_t param,