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radv: Emulate VGT_ESGS_ITEMSIZE in shaders on GFX9+.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21434>
This commit is contained in:
Timur Kristóf
2023-02-21 00:30:21 +01:00
committed by Marge Bot
parent 8aff7152a0
commit 05e6d945ad
3 changed files with 18 additions and 8 deletions
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10
src/amd/vulkan/radv_nir_lower_abi.c
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@@ -281,10 +281,14 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
replacement = nir_imm_int(b, io_num * 16); replacement = nir_imm_int(b, io_num * 16);
break; break;
} }
case nir_intrinsic_load_esgs_vertex_stride_amd: case nir_intrinsic_load_esgs_vertex_stride_amd: {
/* TODO: pass the value of VGT_ESGS_RING_ITEMSIZE here and set the register to 1. */ /* Emulate VGT_ESGS_RING_ITEMSIZE on GFX9+ to reduce context register writes. */
replacement = nir_imm_int(b, 1); assert(s->gfx_level >= GFX9);
const unsigned stride = s->info->is_ngg ? s->info->ngg_info.vgt_esgs_ring_itemsize
: s->info->gs_ring_info.vgt_esgs_ring_itemsize;
replacement = nir_imm_int(b, stride);
break; break;
}
case nir_intrinsic_load_hs_out_patch_data_offset_amd: { case nir_intrinsic_load_hs_out_patch_data_offset_amd: {
unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out; unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out;
unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ? unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ?

12
src/amd/vulkan/radv_pipeline.c
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@@ -3977,9 +3977,6 @@ radv_pipeline_emit_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs
S_028A84_PRIMITIVEID_EN(es_enable_prim_id) | S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id)); S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
ngg_state->vgt_esgs_ring_itemsize);
/* NGG specific registers. */ /* NGG specific registers. */
struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY]; struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1; uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
@@ -4180,8 +4177,13 @@ radv_pipeline_emit_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0)); S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0));
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, if (pdevice->rad_info.gfx_level <= GFX8) {
gs_state->vgt_esgs_ring_itemsize); /* GFX6-8: ESGS offchip ring buffer is allocated according to VGT_ESGS_RING_ITEMSIZE.
* GFX9+: Only used to set the GS input VGPRs, emulated in shaders.
*/
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
gs_state->vgt_esgs_ring_itemsize);
}
va = radv_shader_get_va(gs); va = radv_shader_get_va(gs);

4
src/amd/vulkan/si_cmd_buffer.c
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@@ -214,6 +214,10 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
if (physical_device->rad_info.gfx_level <= GFX8) if (physical_device->rad_info.gfx_level <= GFX8)
si_set_raster_config(physical_device, cs); si_set_raster_config(physical_device, cs);
/* Emulated in shader code on GFX9+. */
if (physical_device->rad_info.gfx_level >= GFX9)
radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 1);
radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
if (!has_clear_state) if (!has_clear_state)
radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));