intel/nir: Set lower txs with non-zero LOD

There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes.  The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds.  Fortunately, not many shaders
actually use textureSize() with LOD.

Shader-db results on Ice Lake:

    total instructions in shared programs: 19948537 -> 19948564 (<.01%)
    instructions in affected programs: 3859 -> 3886 (0.70%)
    helped: 0
    HURT: 7

One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>

src/intel/compiler/brw_nir.c

@@ -828,6 +828,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
       .lower_txd_shadow_clamp = true,
       .lower_txd_offset_clamp = true,
       .lower_tg4_offsets = true,
+      .lower_txs_lod = true, /* Wa_14012320009 */
    };
 
    OPT(nir_lower_tex, &tex_options);