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intel/fs: Make the result of is_unordered() dependent on devinfo.

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Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20072>
This commit is contained in:
Francisco Jerez
2022-02-18 21:58:24 -08:00
committed by Marge Bot
parent d608706875
commit 051887fbf3
3 changed files with 12 additions and 11 deletions
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4
src/intel/compiler/brw_fs_lower_regioning.cpp
View File

@@ -207,7 +207,7 @@ namespace {
has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst,
unsigned i)
{
if (is_unordered(inst) || inst->is_control_source(i))
if (is_send(inst) || inst->is_math() || inst->is_control_source(i))
return false;
/* Empirical testing shows that Broadwell has a bug affecting half-float
@@ -248,7 +248,7 @@ namespace {
has_invalid_dst_region(const intel_device_info *devinfo,
const fs_inst *inst)
{
if (is_unordered(inst)) {
if (is_send(inst) || inst->is_math()) {
return false;
} else {
const brw_reg_type exec_type = get_exec_type(inst);

15
src/intel/compiler/brw_fs_scoreboard.cpp
View File

@@ -112,7 +112,7 @@ namespace {
(inst->opcode == BRW_OPCODE_MAD &&
MIN2(type_sz(inst->src[1].type), type_sz(inst->src[2].type)) >= 4));
if (is_unordered(inst))
if (is_unordered(devinfo, inst))
return TGL_PIPE_NONE;
else if (devinfo->verx10 < 125)
return TGL_PIPE_FLOAT;
@@ -173,7 +173,8 @@ namespace {
* (again) don't use virtual instructions if you want optimal
* scheduling.
*/
if (!is_unordered(inst) && (p == IDX(inferred_exec_pipe(devinfo, inst)) ||
if (!is_unordered(devinfo, inst) &&
(p == IDX(inferred_exec_pipe(devinfo, inst)) ||
p == IDX(TGL_PIPE_ALL)))
return 1;
else
@@ -623,7 +624,7 @@ namespace {
dependency_for_write(const struct intel_device_info *devinfo,
const fs_inst *inst, dependency dep)
{
if (!is_unordered(inst) &&
if (!is_unordered(devinfo, inst) &&
is_single_pipe(dep.jp, inferred_exec_pipe(devinfo, inst)))
dep.ordered &= TGL_REGDIST_DST;
return dep;
@@ -942,7 +943,7 @@ namespace {
if (find_unordered_dependency(deps, TGL_SBID_SET, exec_all))
return find_unordered_dependency(deps, TGL_SBID_SET, exec_all);
else if (has_ordered && is_unordered(inst))
else if (has_ordered && is_unordered(devinfo, inst))
return TGL_SBID_NULL;
else if (find_unordered_dependency(deps, TGL_SBID_DST, exec_all) &&
(!has_ordered || ordered_pipe == inferred_sync_pipe(devinfo, inst)))
@@ -977,7 +978,7 @@ namespace {
return true;
else
return ordered_pipe == inferred_sync_pipe(devinfo, inst) &&
unordered_mode == (is_unordered(inst) ? TGL_SBID_SET :
unordered_mode == (is_unordered(devinfo, inst) ? TGL_SBID_SET :
TGL_SBID_DST);
}
@@ -1032,7 +1033,7 @@ namespace {
/* Track any destination registers of this instruction. */
const dependency wr_dep =
is_unordered(inst) ? dependency(TGL_SBID_DST, ip, exec_all) :
is_unordered(devinfo, inst) ? dependency(TGL_SBID_DST, ip, exec_all) :
is_ordered ? dependency(TGL_REGDIST_DST, jp, exec_all) :
dependency();
@@ -1158,7 +1159,7 @@ namespace {
sb.get(brw_uvec_mrf(8, inst->base_mrf + j, 0))));
}
if (is_unordered(inst) && !inst->eot)
if (is_unordered(devinfo, inst) && !inst->eot)
add_dependency(ids, deps[ip],
dependency(TGL_SBID_SET, ip, exec_all));

2
src/intel/compiler/brw_ir_fs.h
View File

@@ -546,7 +546,7 @@ is_send(const fs_inst *inst)
* assumed to complete in-order.
*/
static inline bool
is_unordered(const fs_inst *inst)
is_unordered(const intel_device_info *devinfo, const fs_inst *inst)
{
return is_send(inst) || inst->is_math();
}