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radv: fix missing initialization of radv_resolve_barrier::dst_stage_mask

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Otherwise, this value is unitialized when read in
radv_ace_internal_barrier().

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7909
Fixes: 4c6f83006d ("radv: Synchronization for task shaders.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20351>
This commit is contained in:
Samuel Pitoiset
2022-12-16 08:12:50 +01:00
parent fc0e23b6dd
commit 050c39c92f
2 changed files with 3 additions and 0 deletions
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src/amd/vulkan/radv_meta_resolve_fs.c
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@@ -895,6 +895,7 @@ radv_cmd_buffer_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer)
/* Resolves happen before rendering ends, so we have to make the attachment shader-readable */
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
barrier.dst_stage_mask = VK_PIPELINE_STAGE_2_RESOLVE_BIT;
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
radv_emit_resolve_barrier(cmd_buffer, &barrier);
@@ -968,6 +969,7 @@ radv_depth_stencil_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer,
/* Resolves happen before rendering ends, so we have to make the attachment shader-readable */
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
barrier.dst_stage_mask = VK_PIPELINE_STAGE_2_RESOLVE_BIT;
barrier.src_access_mask = VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
radv_emit_resolve_barrier(cmd_buffer, &barrier);