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intel: Make engine related functions and types not i915 dependent

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There is too much i915_drm.h code spread, this patch start to fix that
by re-organizing engine related code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18942>
This commit is contained in:
José Roberto de Souza
2022-08-08 11:25:26 -07:00
committed by Marge Bot
parent 24bc3b7644
commit 03b959286e
17 changed files with 223 additions and 99 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/gallium/drivers/iris/iris_batch.c
View File

@@ -272,30 +272,29 @@ iris_create_engines_context(struct iris_context *ice, int priority)
const struct intel_device_info *devinfo = &screen->devinfo;
int fd = iris_bufmgr_get_fd(screen->bufmgr);
struct drm_i915_query_engine_info *engines_info =
intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO, NULL);
struct intel_query_engine_info *engines_info = intel_engine_get_info(fd);
if (!engines_info)
return -1;
if (intel_gem_count_engines(engines_info, I915_ENGINE_CLASS_RENDER) < 1) {
if (intel_engines_count(engines_info, INTEL_ENGINE_CLASS_RENDER) < 1) {
free(engines_info);
return -1;
}
STATIC_ASSERT(IRIS_BATCH_COUNT == 3);
uint16_t engine_classes[IRIS_BATCH_COUNT] = {
[IRIS_BATCH_RENDER] = I915_ENGINE_CLASS_RENDER,
[IRIS_BATCH_COMPUTE] = I915_ENGINE_CLASS_RENDER,
[IRIS_BATCH_BLITTER] = I915_ENGINE_CLASS_COPY,
enum intel_engine_class engine_classes[IRIS_BATCH_COUNT] = {
[IRIS_BATCH_RENDER] = INTEL_ENGINE_CLASS_RENDER,
[IRIS_BATCH_COMPUTE] = INTEL_ENGINE_CLASS_RENDER,
[IRIS_BATCH_BLITTER] = INTEL_ENGINE_CLASS_COPY,
};
/* Blitter is only supported on Gfx12+ */
unsigned num_batches = IRIS_BATCH_COUNT - (devinfo->ver >= 12 ? 0 : 1);
if (env_var_as_boolean("INTEL_COMPUTE_CLASS", false) &&
intel_gem_count_engines(engines_info, I915_ENGINE_CLASS_COMPUTE) > 0)
engine_classes[IRIS_BATCH_COMPUTE] = I915_ENGINE_CLASS_COMPUTE;
intel_engines_count(engines_info, INTEL_ENGINE_CLASS_COMPUTE) > 0)
engine_classes[IRIS_BATCH_COMPUTE] = INTEL_ENGINE_CLASS_COMPUTE;
int engines_ctx =
intel_gem_create_context_engines(fd, engines_info, num_batches,

108
src/intel/common/intel_engine.c Normal file
View File

@@ -0,0 +1,108 @@
/*
* Copyright © 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include <stdlib.h>
#include "intel_engine.h"
#include "intel_gem.h"
enum intel_engine_class i915_engine_class_to_intel(enum drm_i915_gem_engine_class i915)
{
switch (i915) {
case I915_ENGINE_CLASS_RENDER:
return INTEL_ENGINE_CLASS_RENDER;
case I915_ENGINE_CLASS_COPY:
return INTEL_ENGINE_CLASS_COPY;
case I915_ENGINE_CLASS_VIDEO:
return INTEL_ENGINE_CLASS_VIDEO;
case I915_ENGINE_CLASS_VIDEO_ENHANCE:
return INTEL_ENGINE_CLASS_VIDEO_ENHANCE;
case I915_ENGINE_CLASS_COMPUTE:
return INTEL_ENGINE_CLASS_COMPUTE;
default:
return INTEL_ENGINE_CLASS_INVALID;
}
}
enum drm_i915_gem_engine_class intel_engine_class_to_i915(enum intel_engine_class intel)
{
switch (intel) {
case INTEL_ENGINE_CLASS_RENDER:
return I915_ENGINE_CLASS_RENDER;
case INTEL_ENGINE_CLASS_COPY:
return I915_ENGINE_CLASS_COPY;
case INTEL_ENGINE_CLASS_VIDEO:
return I915_ENGINE_CLASS_VIDEO;
case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
return I915_ENGINE_CLASS_VIDEO_ENHANCE;
case INTEL_ENGINE_CLASS_COMPUTE:
return I915_ENGINE_CLASS_COMPUTE;
default:
return I915_ENGINE_CLASS_INVALID;
}
}
struct intel_query_engine_info *
intel_engine_get_info(int fd)
{
struct drm_i915_query_engine_info *i915_engines_info;
i915_engines_info = intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO, NULL);
if (!i915_engines_info)
return NULL;
struct intel_query_engine_info *intel_engines_info;
intel_engines_info = calloc(1, sizeof(*intel_engines_info) +
sizeof(*intel_engines_info->engines) *
i915_engines_info->num_engines);
if (!intel_engines_info) {
free(i915_engines_info);
return NULL;
}
for (int i = 0; i < i915_engines_info->num_engines; i++) {
struct drm_i915_engine_info *i915_engine = &i915_engines_info->engines[i];
struct intel_engine_class_instance *intel_engine = &intel_engines_info->engines[i];
intel_engine->engine_class = i915_engine_class_to_intel(i915_engine->engine.engine_class);
intel_engine->engine_instance = i915_engine->engine.engine_instance;
}
intel_engines_info->num_engines = i915_engines_info->num_engines;
free(i915_engines_info);
return intel_engines_info;
}
int
intel_engines_count(const struct intel_query_engine_info *info,
enum intel_engine_class engine_class)
{
int count = 0;
for (int i = 0; i < info->num_engines; i++) {
if (info->engines[i].engine_class == engine_class)
count++;
}
return count;
}

54
src/intel/common/intel_engine.h Normal file
View File

@@ -0,0 +1,54 @@
/*
* Copyright © 2022 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#pragma once
#include <stdint.h>
#include "drm-uapi/i915_drm.h"
enum intel_engine_class {
INTEL_ENGINE_CLASS_RENDER = 0,
INTEL_ENGINE_CLASS_COPY,
INTEL_ENGINE_CLASS_VIDEO,
INTEL_ENGINE_CLASS_VIDEO_ENHANCE,
INTEL_ENGINE_CLASS_COMPUTE,
INTEL_ENGINE_CLASS_INVALID
};
struct intel_engine_class_instance {
enum intel_engine_class engine_class;
uint16_t engine_instance;
};
struct intel_query_engine_info {
uint32_t num_engines;
struct intel_engine_class_instance engines[];
};
enum intel_engine_class i915_engine_class_to_intel(enum drm_i915_gem_engine_class i915);
enum drm_i915_gem_engine_class intel_engine_class_to_i915(enum intel_engine_class intel);
struct intel_query_engine_info *intel_engine_get_info(int fd);
int intel_engines_count(const struct intel_query_engine_info *info,
enum intel_engine_class engine_class);

54
src/intel/common/intel_gem.c
View File

@@ -58,23 +58,10 @@ intel_gem_supports_syncobj_wait(int fd)
return ret == -1 && errno == ETIME;
}
int
intel_gem_count_engines(const struct drm_i915_query_engine_info *info,
enum drm_i915_gem_engine_class engine_class)
{
assert(info != NULL);
int count = 0;
for (int i = 0; i < info->num_engines; i++) {
if (info->engines[i].engine.engine_class == engine_class)
count++;
}
return count;
}
int
intel_gem_create_context_engines(int fd,
const struct drm_i915_query_engine_info *info,
int num_engines, uint16_t *engine_classes)
const struct intel_query_engine_info *info,
int num_engines, enum intel_engine_class *engine_classes)
{
assert(info != NULL);
assert(num_engines <= 64);
@@ -85,31 +72,30 @@ intel_gem_create_context_engines(int fd,
* the previous engine instance used.
*/
int last_engine_idx[] = {
[I915_ENGINE_CLASS_RENDER] = -1,
[I915_ENGINE_CLASS_COPY] = -1,
[I915_ENGINE_CLASS_COMPUTE] = -1,
[INTEL_ENGINE_CLASS_RENDER] = -1,
[INTEL_ENGINE_CLASS_COPY] = -1,
[INTEL_ENGINE_CLASS_COMPUTE] = -1,
};
int i915_engine_counts[] = {
[I915_ENGINE_CLASS_RENDER] =
intel_gem_count_engines(info, I915_ENGINE_CLASS_RENDER),
[I915_ENGINE_CLASS_COPY] =
intel_gem_count_engines(info, I915_ENGINE_CLASS_COPY),
[I915_ENGINE_CLASS_COMPUTE] =
intel_gem_count_engines(info, I915_ENGINE_CLASS_COMPUTE),
int engine_counts[] = {
[INTEL_ENGINE_CLASS_RENDER] =
intel_engines_count(info, INTEL_ENGINE_CLASS_RENDER),
[INTEL_ENGINE_CLASS_COPY] =
intel_engines_count(info, INTEL_ENGINE_CLASS_COPY),
[INTEL_ENGINE_CLASS_COMPUTE] =
intel_engines_count(info, INTEL_ENGINE_CLASS_COMPUTE),
};
/* For each queue, we look for the next instance that matches the class we
* need.
*/
for (int i = 0; i < num_engines; i++) {
uint16_t engine_class = engine_classes[i];
assert(engine_class == I915_ENGINE_CLASS_RENDER ||
engine_class == I915_ENGINE_CLASS_COPY ||
engine_class == I915_ENGINE_CLASS_COMPUTE);
if (i915_engine_counts[engine_class] <= 0) {
enum intel_engine_class engine_class = engine_classes[i];
assert(engine_class == INTEL_ENGINE_CLASS_RENDER ||
engine_class == INTEL_ENGINE_CLASS_COPY ||
engine_class == INTEL_ENGINE_CLASS_COMPUTE);
if (engine_counts[engine_class] <= 0)
return -1;
}
/* Run through the engines reported by the kernel looking for the next
* matching instance. We loop in case we want to create multiple
@@ -120,8 +106,8 @@ intel_gem_create_context_engines(int fd,
int *idx = &last_engine_idx[engine_class];
if (++(*idx) >= info->num_engines)
*idx = 0;
if (info->engines[*idx].engine.engine_class == engine_class) {
engine_instance = info->engines[*idx].engine.engine_instance;
if (info->engines[*idx].engine_class == engine_class) {
engine_instance = info->engines[*idx].engine_instance;
break;
}
}
@@ -129,7 +115,7 @@ intel_gem_create_context_engines(int fd,
return -1;
}
engines_param.engines[i].engine_class = engine_class;
engines_param.engines[i].engine_class = intel_engine_class_to_i915(engine_class);
engines_param.engines[i].engine_instance = engine_instance;
}

8
src/intel/common/intel_gem.h
View File

@@ -38,6 +38,8 @@ extern "C" {
#include <unistd.h>
#include <sys/ioctl.h>
#include "intel_engine.h"
static inline uint64_t
intel_canonical_address(uint64_t v)
{
@@ -156,11 +158,9 @@ intel_i915_query_alloc(int fd, uint64_t query_id, int32_t *query_length)
bool intel_gem_supports_syncobj_wait(int fd);
int intel_gem_count_engines(const struct drm_i915_query_engine_info *info,
enum drm_i915_gem_engine_class engine_class);
int intel_gem_create_context_engines(int fd,
const struct drm_i915_query_engine_info *info,
int num_engines, uint16_t *engine_classes);
const struct intel_query_engine_info *info,
int num_engines, enum intel_engine_class *engine_classes);
bool intel_gem_read_render_timestamp(int fd, uint64_t *value);

2
src/intel/common/meson.build
View File

@@ -26,6 +26,8 @@ files_libintel_common = files(
'intel_decoder.h',
'intel_disasm.c',
'intel_disasm.h',
'intel_engine.c',
'intel_engine.h',
'intel_gem.c',
'intel_gem.h',
'intel_guardband.h',

20
src/intel/vulkan/anv_device.c
View File

@@ -679,15 +679,15 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
if (pdevice->engine_info) {
int gc_count =
intel_gem_count_engines(pdevice->engine_info,
I915_ENGINE_CLASS_RENDER);
intel_engines_count(pdevice->engine_info,
INTEL_ENGINE_CLASS_RENDER);
int g_count = 0;
int c_count = 0;
if (env_var_as_boolean("INTEL_COMPUTE_CLASS", false))
c_count = intel_gem_count_engines(pdevice->engine_info,
I915_ENGINE_CLASS_COMPUTE);
c_count = intel_engines_count(pdevice->engine_info,
INTEL_ENGINE_CLASS_COMPUTE);
enum drm_i915_gem_engine_class compute_class =
c_count < 1 ? I915_ENGINE_CLASS_RENDER : I915_ENGINE_CLASS_COMPUTE;
c_count < 1 ? INTEL_ENGINE_CLASS_RENDER : INTEL_ENGINE_CLASS_COMPUTE;
anv_override_engine_counts(&gc_count, &g_count, &c_count);
@@ -697,7 +697,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
VK_QUEUE_COMPUTE_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = gc_count,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
}
if (g_count > 0) {
@@ -705,7 +705,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
.queueFlags = VK_QUEUE_GRAPHICS_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = g_count,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
}
if (c_count > 0) {
@@ -727,7 +727,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
VK_QUEUE_COMPUTE_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = 1,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
family_count = 1;
}
@@ -955,7 +955,7 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
}
device->master_fd = master_fd;
device->engine_info = anv_gem_get_engine_info(fd);
device->engine_info = intel_engine_get_info(fd);
anv_physical_device_init_queue_families(device);
device->local_fd = fd;
@@ -3088,7 +3088,7 @@ anv_device_setup_context(struct anv_device *device,
if (device->physical->engine_info) {
/* The kernel API supports at most 64 engines */
assert(num_queues <= 64);
uint16_t engine_classes[64];
enum intel_engine_class engine_classes[64];
int engine_count = 0;
for (uint32_t i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
const VkDeviceQueueCreateInfo *queueCreateInfo =

6
src/intel/vulkan/anv_gem.c
View File

@@ -384,9 +384,3 @@ anv_gem_fd_to_handle(struct anv_device *device, int fd)
return args.handle;
}
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{
return intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO, NULL);
}

6
src/intel/vulkan/anv_gem_stubs.c
View File

@@ -173,9 +173,3 @@ anv_i915_query(int fd, uint64_t query_id, void *buffer,
{
unreachable("Unused");
}
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{
unreachable("Unused");
}

2
src/intel/vulkan/anv_perf.c
View File

@@ -343,7 +343,7 @@ VkResult anv_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR(
*/
struct anv_queue_family *queue_family =
&pdevice->queue.families[queueFamilyIndex];
if (queue_family->engine_class != I915_ENGINE_CLASS_RENDER)
if (queue_family->engine_class != INTEL_ENGINE_CLASS_RENDER)
return vk_outarray_status(&out);
for (int c = 0; c < (perf ? perf->n_counters : 0); c++) {

7
src/intel/vulkan/anv_private.h
View File

@@ -43,6 +43,7 @@
#include "common/intel_clflush.h"
#include "common/intel_decoder.h"
#include "common/intel_engine.h"
#include "common/intel_gem.h"
#include "common/intel_l3_config.h"
#include "common/intel_measure.h"
@@ -927,8 +928,7 @@ struct anv_queue_family {
VkQueueFlags queueFlags;
uint32_t queueCount;
/* Driver internal information */
enum drm_i915_gem_engine_class engine_class;
enum intel_engine_class engine_class;
};
#define ANV_MAX_QUEUE_FAMILIES 3
@@ -1053,7 +1053,7 @@ struct anv_physical_device {
bool has_master;
int64_t master_major;
int64_t master_minor;
struct drm_i915_query_engine_info * engine_info;
struct intel_query_engine_info * engine_info;
void (*cmd_emit_timestamp)(struct anv_batch *, struct anv_device *, struct anv_address, bool);
struct intel_measure_device measure_device;
@@ -1374,7 +1374,6 @@ uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
int anv_i915_query(int fd, uint64_t query_id, void *buffer,
int32_t *buffer_len);
struct drm_i915_query_engine_info *anv_gem_get_engine_info(int fd);
uint64_t anv_vma_alloc(struct anv_device *device,
uint64_t size, uint64_t align,

8
src/intel/vulkan/anv_utrace.c
View File

@@ -267,13 +267,13 @@ static const char *
queue_family_to_name(const struct anv_queue_family *family)
{
switch (family->engine_class) {
case I915_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_RENDER:
return "render";
case I915_ENGINE_CLASS_COPY:
case INTEL_ENGINE_CLASS_COPY:
return "copy";
case I915_ENGINE_CLASS_VIDEO:
case INTEL_ENGINE_CLASS_VIDEO:
return "video";
case I915_ENGINE_CLASS_VIDEO_ENHANCE:
case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
return "video-enh";
default:
return "unknown";

4
src/intel/vulkan/genX_state.c
View File

@@ -472,10 +472,10 @@ genX(init_device_state)(struct anv_device *device)
for (uint32_t i = 0; i < device->queue_count; i++) {
struct anv_queue *queue = &device->queues[i];
switch (queue->family->engine_class) {
case I915_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_RENDER:
res = init_render_queue_state(queue);
break;
case I915_ENGINE_CLASS_COMPUTE:
case INTEL_ENGINE_CLASS_COMPUTE:
res = init_compute_queue_state(queue);
break;
default:

10
src/intel/vulkan_hasvk/anv_device.c
View File

@@ -675,8 +675,8 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
if (pdevice->engine_info) {
int gc_count =
intel_gem_count_engines(pdevice->engine_info,
I915_ENGINE_CLASS_RENDER);
intel_engines_count(pdevice->engine_info,
INTEL_ENGINE_CLASS_RENDER);
int g_count = 0;
int c_count = 0;
@@ -688,7 +688,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
VK_QUEUE_COMPUTE_BIT |
VK_QUEUE_TRANSFER_BIT,
.queueCount = gc_count,
.engine_class = I915_ENGINE_CLASS_RENDER,
.engine_class = INTEL_ENGINE_CLASS_RENDER,
};
}
if (g_count > 0) {
@@ -991,7 +991,7 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
}
device->master_fd = master_fd;
device->engine_info = anv_gem_get_engine_info(fd);
device->engine_info = intel_engine_get_info(fd);
anv_physical_device_init_queue_families(device);
device->local_fd = fd;
@@ -2879,7 +2879,7 @@ anv_device_setup_context(struct anv_device *device,
if (device->physical->engine_info) {
/* The kernel API supports at most 64 engines */
assert(num_queues <= 64);
uint16_t engine_classes[64];
enum intel_engine_class engine_classes[64];
int engine_count = 0;
for (uint32_t i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
const VkDeviceQueueCreateInfo *queueCreateInfo =

6
src/intel/vulkan_hasvk/anv_gem.c
View File

@@ -384,9 +384,3 @@ anv_gem_fd_to_handle(struct anv_device *device, int fd)
return args.handle;
}
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{
return intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO, NULL);
}

6
src/intel/vulkan_hasvk/anv_gem_stubs.c
View File

@@ -173,9 +173,3 @@ anv_i915_query(int fd, uint64_t query_id, void *buffer,
{
unreachable("Unused");
}
struct drm_i915_query_engine_info *
anv_gem_get_engine_info(int fd)
{
unreachable("Unused");
}

4
src/intel/vulkan_hasvk/anv_private.h
View File

@@ -43,6 +43,7 @@
#include "common/intel_clflush.h"
#include "common/intel_decoder.h"
#include "common/intel_engine.h"
#include "common/intel_gem.h"
#include "common/intel_l3_config.h"
#include "common/intel_measure.h"
@@ -1061,7 +1062,7 @@ struct anv_physical_device {
bool has_master;
int64_t master_major;
int64_t master_minor;
struct drm_i915_query_engine_info * engine_info;
struct intel_query_engine_info * engine_info;
void (*cmd_emit_timestamp)(struct anv_batch *, struct anv_device *, struct anv_address, bool);
struct intel_measure_device measure_device;
@@ -1439,7 +1440,6 @@ uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
int anv_i915_query(int fd, uint64_t query_id, void *buffer,
int32_t *buffer_len);
struct drm_i915_query_engine_info *anv_gem_get_engine_info(int fd);
uint64_t anv_vma_alloc(struct anv_device *device,
uint64_t size, uint64_t align,