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ac/nir: Move some helpers to new file.

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Also remove nir_builder include from ac_nir.h.
This is done so that driver code doesn't need to be recompiled
when some internal parts of ac/nir in the new helper header
is changed.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28936>
This commit is contained in:
Timur Kristóf
2024-04-25 16:14:11 +02:00
parent cd66b77af0
commit 039e739eea
9 changed files with 120 additions and 80 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/amd/common/ac_nir.c
View File

@@ -5,6 +5,7 @@
*/
#include "ac_nir.h"
#include "ac_nir_helpers.h"
#include "sid.h"
#include "nir_builder.h"
#include "nir_xfb_info.h"
@@ -1410,7 +1411,7 @@ split_pack_half(nir_builder *b, nir_instr *instr, void *param)
b->cursor = nir_before_instr(instr);
/* Split pack_half into two f2f16 to create v_fma_mix{lo,hi}_f16
/* Split pack_half into two f2f16 to create v_fma_mix{lo,hi}_f16
* in the backend.
*/
nir_def *lo = nir_f2f16(b, nir_ssa_for_alu_src(b, alu, 0));

79
src/amd/common/ac_nir.h
View File

@@ -12,7 +12,6 @@
#include "ac_shader_args.h"
#include "ac_shader_util.h"
#include "nir.h"
#include "nir_builder.h"
#ifdef __cplusplus
extern "C" {
@@ -70,47 +69,6 @@ bool ac_nir_lower_intrinsics_to_args(nir_shader *shader, const enum amd_gfx_leve
const enum ac_hw_stage hw_stage,
const struct ac_shader_args *ac_args);
void
ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value,
unsigned component, unsigned writemask);
void
ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row);
void
ac_nir_export_position(nir_builder *b,
enum amd_gfx_level gfx_level,
uint32_t clip_cull_mask,
bool no_param_export,
bool force_vrs,
bool done,
uint64_t outputs_written,
nir_def *(*outputs)[4],
nir_def *row);
void
ac_nir_export_parameters(nir_builder *b,
const uint8_t *param_offsets,
uint64_t outputs_written,
uint16_t outputs_written_16bit,
nir_def *(*outputs)[4],
nir_def *(*outputs_16bit_lo)[4],
nir_def *(*outputs_16bit_hi)[4]);
nir_def *
ac_nir_calc_io_offset(nir_builder *b,
nir_intrinsic_instr *intrin,
nir_def *base_stride,
unsigned component_stride,
ac_nir_map_io_driver_location map_io);
nir_def *
ac_nir_calc_io_offset_mapped(nir_builder *b,
nir_intrinsic_instr *intrin,
nir_def *base_stride,
unsigned component_stride,
unsigned mapped_location);
bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS],
uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]);
@@ -218,14 +176,6 @@ ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader,
unsigned task_payload_entry_bytes,
unsigned task_num_entries);
nir_def *
ac_nir_cull_primitive(nir_builder *b,
nir_def *initially_accepted,
nir_def *pos[3][4],
unsigned num_vertices,
ac_nir_cull_accepted accept_func,
void *state);
bool
ac_nir_lower_global_access(nir_shader *shader);
@@ -361,35 +311,6 @@ ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4);
bool
ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level);
#define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \
do { \
if ((store_val)->bit_size >= 32) { \
const unsigned store_write_mask = (write_mask); \
const unsigned store_const_offset = (const_offset); \
func((b), (store_val), __VA_ARGS__); \
} else { \
u_foreach_bit(c, (write_mask)) { \
const unsigned store_write_mask = 1; \
const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \
nir_def *store_component = nir_channel(b, (store_val), c); \
func((b), store_component, __VA_ARGS__); \
} \
} \
} while (0)
#define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \
do { \
const unsigned load_bit_size = MAX2(32, (bit_size)); \
(load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \
if ((bit_size) < load_bit_size) { \
if ((hi_16bit)) { \
(load) = nir_unpack_32_2x16_split_y(b, load); \
} else { \
(load) = nir_unpack_32_2x16_split_x(b, load); \
} \
} \
} while (0)
#ifdef __cplusplus
}
#endif

1
src/amd/common/ac_nir_cull.c
View File

@@ -6,6 +6,7 @@
*/
#include "ac_nir.h"
#include "ac_nir_helpers.h"
#include "nir_builder.h"
/* This code is adapted from ac_llvm_cull.c, hence the copyright to AMD. */

112
src/amd/common/ac_nir_helpers.h Normal file
View File

@@ -0,0 +1,112 @@
/*
* Copyright © 2024 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#ifndef AC_NIR_HELPERS_H
#define AC_NIR_HELPERS_H
#include "ac_hw_stage.h"
#include "ac_shader_args.h"
#include "ac_shader_util.h"
#include "nir.h"
#ifdef __cplusplus
extern "C" {
#endif
#define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \
do { \
if ((store_val)->bit_size >= 32) { \
const unsigned store_write_mask = (write_mask); \
const unsigned store_const_offset = (const_offset); \
func((b), (store_val), __VA_ARGS__); \
} else { \
u_foreach_bit(c, (write_mask)) { \
const unsigned store_write_mask = 1; \
const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \
nir_def *store_component = nir_channel(b, (store_val), c); \
func((b), store_component, __VA_ARGS__); \
} \
} \
} while (0)
#define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \
do { \
const unsigned load_bit_size = MAX2(32, (bit_size)); \
(load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \
if ((bit_size) < load_bit_size) { \
if ((hi_16bit)) { \
(load) = nir_unpack_32_2x16_split_y(b, load); \
} else { \
(load) = nir_unpack_32_2x16_split_x(b, load); \
} \
} \
} while (0)
/* Maps I/O semantics to the actual location used by the lowering pass. */
typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic);
/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */
struct nir_builder;
typedef struct nir_builder nir_builder;
/* Executed by ac_nir_cull when the current primitive is accepted. */
typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state);
void
ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value,
unsigned component, unsigned writemask);
void
ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row);
void
ac_nir_export_position(nir_builder *b,
enum amd_gfx_level gfx_level,
uint32_t clip_cull_mask,
bool no_param_export,
bool force_vrs,
bool done,
uint64_t outputs_written,
nir_def *(*outputs)[4],
nir_def *row);
void
ac_nir_export_parameters(nir_builder *b,
const uint8_t *param_offsets,
uint64_t outputs_written,
uint16_t outputs_written_16bit,
nir_def *(*outputs)[4],
nir_def *(*outputs_16bit_lo)[4],
nir_def *(*outputs_16bit_hi)[4]);
nir_def *
ac_nir_calc_io_offset(nir_builder *b,
nir_intrinsic_instr *intrin,
nir_def *base_stride,
unsigned component_stride,
ac_nir_map_io_driver_location map_io);
nir_def *
ac_nir_calc_io_offset_mapped(nir_builder *b,
nir_intrinsic_instr *intrin,
nir_def *base_stride,
unsigned component_stride,
unsigned mapped_location);
nir_def *
ac_nir_cull_primitive(nir_builder *b,
nir_def *initially_accepted,
nir_def *pos[3][4],
unsigned num_vertices,
ac_nir_cull_accepted accept_func,
void *state);
#ifdef __cplusplus
}
#endif
#endif /* AC_NIR_HELPERS_H */

1
src/amd/common/ac_nir_lower_esgs_io_to_mem.c
View File

@@ -5,6 +5,7 @@
*/
#include "ac_nir.h"
#include "ac_nir_helpers.h"
#include "nir_builder.h"
/*

1
src/amd/common/ac_nir_lower_ngg.c
View File

@@ -5,6 +5,7 @@
*/
#include "ac_nir.h"
#include "ac_nir_helpers.h"
#include "amdgfxregs.h"
#include "nir_builder.h"
#include "nir_xfb_info.h"

1
src/amd/common/ac_nir_lower_subdword_loads.c
View File

@@ -23,6 +23,7 @@
#include "util/u_math.h"
#include "ac_nir.h"
#include "nir_builder.h"
static bool
lower_subdword_loads(nir_builder *b, nir_instr *instr, void *data)

1
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View File

@@ -5,6 +5,7 @@
*/
#include "ac_nir.h"
#include "ac_nir_helpers.h"
#include "nir_builder.h"
/*

1
src/amd/common/meson.build
View File

@@ -92,6 +92,7 @@ amd_common_files = files(
'ac_msgpack.h',
'ac_nir.c',
'ac_nir.h',
'ac_nir_helpers.h',
'ac_nir_opt_outputs.c',
'ac_nir_cull.c',
'ac_nir_lower_esgs_io_to_mem.c',