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radv: add support for executing the DGC ACE IB

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It's disabled for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
This commit is contained in:
Samuel Pitoiset
2024-06-20 17:48:49 +02:00
committed by Marge Bot
parent 1e0c6fab21
commit 037eaa962b
3 changed files with 33 additions and 0 deletions
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13
src/amd/vulkan/radv_cmd_buffer.c
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@@ -11510,14 +11510,27 @@ static void radv_dgc_after_dispatch(struct radv_cmd_buffer *cmd_buffer);
static void
radv_dgc_execute_ib(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsInfoNV *pGeneratedCommandsInfo)
{
VK_FROM_HANDLE(radv_indirect_command_layout, layout, pGeneratedCommandsInfo->indirectCommandsLayout);
VK_FROM_HANDLE(radv_buffer, prep_buffer, pGeneratedCommandsInfo->preprocessBuffer);
VK_FROM_HANDLE(radv_pipeline, pipeline, pGeneratedCommandsInfo->pipeline);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const bool has_task_shader = layout->pipeline_bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
pipeline->shaders[MESA_SHADER_TASK] && false /* TODO: Enable when fully implemented */;
const uint32_t cmdbuf_size = radv_get_indirect_cmdbuf_size(pGeneratedCommandsInfo);
const uint64_t ib_va =
radv_buffer_get_va(prep_buffer->bo) + prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
device->ws->cs_execute_ib(cmd_buffer->cs, NULL, ib_va, cmdbuf_size >> 2, cmd_buffer->state.predicating);
if (has_task_shader) {
const uint32_t ace_cmdbuf_size = radv_get_indirect_ace_cmdbuf_size(pGeneratedCommandsInfo);
const uint64_t ace_ib_va = ib_va + radv_get_indirect_ace_cmdbuf_offset(pGeneratedCommandsInfo);
assert(cmd_buffer->gang.cs);
device->ws->cs_execute_ib(cmd_buffer->gang.cs, NULL, ace_ib_va, ace_cmdbuf_size >> 2,
cmd_buffer->state.predicating);
}
}
VKAPI_ATTR void VKAPI_CALL

18
src/amd/vulkan/radv_device_generated_commands.c
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@@ -236,6 +236,24 @@ radv_get_indirect_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
return radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount, AMD_IP_GFX);
}
uint32_t
radv_get_indirect_ace_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info)
{
VK_FROM_HANDLE(radv_indirect_command_layout, layout, cmd_info->indirectCommandsLayout);
VK_FROM_HANDLE(radv_pipeline, pipeline, cmd_info->pipeline);
const struct radv_device *device = container_of(layout->base.device, struct radv_device, vk);
uint32_t cmd_size, ace_cmd_size, upload_size;
radv_get_sequence_size(layout, pipeline, &cmd_size, &ace_cmd_size, &upload_size);
uint32_t offset = radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount, AMD_IP_GFX);
if (radv_dgc_use_preamble(cmd_info))
offset += radv_dgc_preamble_cmdbuf_size(device, AMD_IP_GFX);
return offset;
}
uint32_t
radv_get_indirect_ace_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
{

2
src/amd/vulkan/radv_device_generated_commands.h
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@@ -58,6 +58,8 @@ uint32_t radv_get_indirect_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info
uint32_t radv_get_indirect_ace_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_ace_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info);
bool radv_use_dgc_predication(struct radv_cmd_buffer *cmd_buffer,
const VkGeneratedCommandsInfoNV *pGeneratedCommandsInfo);