freedreno/ir3: Add intrinsics that map to LDLW/STLW
These intrinsics will let us do all the offset calculations in nir, which is nicer to work with and lets nir_opt_algebraic eat it all up. Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
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@@ -771,6 +771,14 @@ intrinsic("ssbo_atomic_xor_ir3", src_comp=[1, 1, 1, 1], dest_comp=1)
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intrinsic("ssbo_atomic_exchange_ir3", src_comp=[1, 1, 1, 1], dest_comp=1)
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intrinsic("ssbo_atomic_comp_swap_ir3", src_comp=[1, 1, 1, 1, 1], dest_comp=1)
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# IR3-specific load/store intrinsics. These access a buffer used to pass data
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# between geometry stages - perhaps it's explicit access to the vertex cache.
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# src[] = { value, offset }.
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store("shared_ir3", 2, [BASE, WRMASK, ALIGN_MUL, ALIGN_OFFSET])
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# src[] = { offset }.
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load("shared_ir3", 1, [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE])
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# Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined
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# within a blend shader to read/write the raw value from the tile buffer,
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# without applying any format conversion in the process. If the shader needs
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@@ -843,6 +843,75 @@ emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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}
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}
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/* src[] = { offset }. const_index[] = { base } */
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static void
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emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *load, *offset;
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unsigned base;
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offset = ir3_get_src(ctx, &intr->src[0])[0];
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base = nir_intrinsic_base(intr);
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load = ir3_LDLW(b, offset, 0,
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create_immed(b, intr->num_components), 0,
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create_immed(b, base), 0);
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load->cat6.type = utype_dst(intr->dest);
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load->regs[0]->wrmask = MASK(intr->num_components);
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load->barrier_class = IR3_BARRIER_SHARED_R;
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load->barrier_conflict = IR3_BARRIER_SHARED_W;
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ir3_split_dest(b, dst, load, 0, intr->num_components);
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}
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/* src[] = { value, offset }. const_index[] = { base, write_mask } */
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static void
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emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *store, *offset;
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struct ir3_instruction * const *value;
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unsigned base, wrmask;
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value = ir3_get_src(ctx, &intr->src[0]);
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offset = ir3_get_src(ctx, &intr->src[1])[0];
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base = nir_intrinsic_base(intr);
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wrmask = nir_intrinsic_write_mask(intr);
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/* Combine groups of consecutive enabled channels in one write
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* message. We use ffs to find the first enabled channel and then ffs on
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* the bit-inverse, down-shifted writemask to determine the length of
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* the block of enabled bits.
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*
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* (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
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*/
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while (wrmask) {
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unsigned first_component = ffs(wrmask) - 1;
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unsigned length = ffs(~(wrmask >> first_component)) - 1;
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store = ir3_STLW(b, offset, 0,
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ir3_create_collect(ctx, &value[first_component], length), 0,
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create_immed(b, length), 0);
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store->cat6.dst_offset = first_component + base;
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store->cat6.type = utype_src(intr->src[0]);
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store->barrier_class = IR3_BARRIER_SHARED_W;
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store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
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array_insert(b, b->keeps, store);
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/* Clear the bits in the writemask that we just wrote, then try
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* again to see if more channels are left.
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*/
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wrmask &= (15 << (first_component + length));
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}
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}
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/*
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* CS shared variable atomic intrinsics
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*
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@@ -1582,6 +1651,12 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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break;
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}
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case nir_intrinsic_load_shared_ir3:
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emit_intrinsic_load_shared_ir3(ctx, intr, dst);
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break;
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case nir_intrinsic_store_shared_ir3:
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emit_intrinsic_store_shared_ir3(ctx, intr);
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break;
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default:
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ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
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nir_intrinsic_infos[intr->intrinsic].name);
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