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radv: move calculating vs out info regs into pipeline.

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This moves some calculations of register values into the pipeline
construction, it saves looking at outinfo in the cmd buffer emit.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2017-11-06 02:00:34 +00:00
parent 4a9aad96aa
commit 031e591923
3 changed files with 34 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -698,28 +698,15 @@ radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
static void static void
radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer, radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline, struct radv_pipeline *pipeline,
struct radv_shader_variant *shader, struct radv_shader_variant *shader)
struct ac_vs_output_info *outinfo)
{ {
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
unsigned export_count;
export_count = MAX2(1, outinfo->param_exports);
radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG, radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
S_0286C4_VS_EXPORT_COUNT(export_count - 1)); pipeline->graphics.vs.spi_vs_out_config);
radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT, radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | pipeline->graphics.vs.spi_shader_pos_format);
S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE));
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4); radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cmd_buffer->cs, va >> 8); radeon_emit(cmd_buffer->cs, va >> 8);
@@ -735,11 +722,11 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL, radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
pipeline->graphics.pa_cl_vs_out_cntl); pipeline->graphics.vs.pa_cl_vs_out_cntl);
if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI) if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF, radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
S_028AB4_REUSE_OFF(outinfo->writes_viewport_index)); pipeline->graphics.vs.vgt_reuse_off);
} }
static void static void
@@ -821,7 +808,7 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
else if (vs->info.vs.as_es) else if (vs->info.vs.as_es)
radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info); radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
else else
radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo); radv_emit_hw_vs(cmd_buffer, pipeline, vs);
} }
@@ -841,7 +828,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
if (tes->info.tes.as_es) if (tes->info.tes.as_es)
radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info); radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
else else
radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo); radv_emit_hw_vs(cmd_buffer, pipeline, tes);
} }
radv_emit_hw_hs(cmd_buffer, tcs); radv_emit_hw_hs(cmd_buffer, tcs);
@@ -951,7 +938,7 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, gs->rsrc2); radeon_emit(cmd_buffer->cs, gs->rsrc2);
} }
radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo); radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY, struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
AC_UD_GS_VS_RING_STRIDE_ENTRIES); AC_UD_GS_VS_RING_STRIDE_ENTRIES);

21
src/amd/vulkan/radv_pipeline.c
View File

@@ -1545,7 +1545,7 @@ static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
} }
} }
static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline) static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
{ {
struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline); struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
@@ -1557,7 +1557,7 @@ static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
bool misc_vec_ena = outinfo->writes_pointsize || bool misc_vec_ena = outinfo->writes_pointsize ||
outinfo->writes_layer || outinfo->writes_layer ||
outinfo->writes_viewport_index; outinfo->writes_viewport_index;
pipeline->graphics.pa_cl_vs_out_cntl = pipeline->graphics.vs.pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) | S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
@@ -1568,6 +1568,21 @@ static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
cull_dist_mask << 8 | cull_dist_mask << 8 |
clip_dist_mask; clip_dist_mask;
pipeline->graphics.vs.spi_shader_pos_format =
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE) |
S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE);
pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1);
/* only emitted on pre-VI */
pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index);
} }
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade) static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
@@ -2093,7 +2108,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
V_028710_SPI_SHADER_ZERO; V_028710_SPI_SHADER_ZERO;
calculate_vgt_gs_mode(pipeline); calculate_vgt_gs_mode(pipeline);
calculate_pa_cl_vs_out_cntl(pipeline); calculate_vs_outinfo(pipeline);
calculate_ps_inputs(pipeline); calculate_ps_inputs(pipeline);
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {

9
src/amd/vulkan/radv_private.h
View File

@@ -1110,6 +1110,13 @@ struct radv_vertex_elements_info {
uint32_t count; uint32_t count;
}; };
struct radv_vs_state {
uint32_t pa_cl_vs_out_cntl;
uint32_t spi_shader_pos_format;
uint32_t spi_vs_out_config;
uint32_t vgt_reuse_off;
};
#define SI_GS_PER_ES 128 #define SI_GS_PER_ES 128
struct radv_pipeline { struct radv_pipeline {
@@ -1137,6 +1144,7 @@ struct radv_pipeline {
struct radv_multisample_state ms; struct radv_multisample_state ms;
struct radv_tessellation_state tess; struct radv_tessellation_state tess;
struct radv_gs_state gs; struct radv_gs_state gs;
struct radv_vs_state vs;
uint32_t db_shader_control; uint32_t db_shader_control;
uint32_t shader_z_format; uint32_t shader_z_format;
unsigned prim; unsigned prim;
@@ -1150,7 +1158,6 @@ struct radv_pipeline {
unsigned gsvs_ring_size; unsigned gsvs_ring_size;
uint32_t ps_input_cntl[32]; uint32_t ps_input_cntl[32];
uint32_t ps_input_cntl_num; uint32_t ps_input_cntl_num;
uint32_t pa_cl_vs_out_cntl;
uint32_t vgt_shader_stages_en; uint32_t vgt_shader_stages_en;
uint32_t vtx_base_sgpr; uint32_t vtx_base_sgpr;
uint32_t base_ia_multi_vgt_param; uint32_t base_ia_multi_vgt_param;