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radv/rt: Get rid of accel struct null checks

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Quake II RTX ray queries:

Totals from 7 (14.29% of 49) affected shaders:
CodeSize: 167220 -> 165560 (-0.99%)
Instrs: 31674 -> 31454 (-0.69%)
Latency: 385145 -> 596737 (+54.94%)
InvThroughput: 78837 -> 122005 (+54.76%)
Copies: 4740 -> 4667 (-1.54%); split: -1.60%, +0.06%
Branches: 1565 -> 1493 (-4.60%)
PreSGPRs: 488 -> 501 (+2.66%); split: -0.41%, +3.07%
PreVGPRs: 617 -> 620 (+0.49%)

Performance stays the same.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20539>
This commit is contained in:
Konstantin Seurer
2023-01-05 17:48:45 +01:00
committed by Marge Bot
parent 33166ba50b
commit 03105138f1
3 changed files with 276 additions and 296 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/amd/vulkan/radv_nir_lower_ray_queries.c
View File

@@ -391,8 +391,6 @@ lower_rq_initialize(nir_builder *b, nir_ssa_def *index, nir_intrinsic_instr *ins
nir_ssa_def *accel_struct = instr->src[1].ssa;
nir_push_if(b, nir_ine_imm(b, accel_struct, 0));
{
nir_ssa_def *bvh_offset = nir_build_load_global(
b, 1, 32,
nir_iadd_imm(b, accel_struct, offsetof(struct radv_accel_struct_header, bvh_offset)),
@@ -413,12 +411,6 @@ lower_rq_initialize(nir_builder *b, nir_ssa_def *index, nir_intrinsic_instr *ins
rq_store_var(b, index, vars->trav.stack, base_offset, 0x1);
rq_store_var(b, index, vars->trav.stack_low_watermark, base_offset, 0x1);
}
}
nir_push_else(b, NULL);
{
rq_store_var(b, index, vars->root_bvh_base, nir_imm_int64(b, 0), 0x1);
}
nir_pop_if(b, NULL);
rq_store_var(b, index, vars->trav.current_node, nir_imm_int(b, RADV_BVH_ROOT_NODE), 0x1);
rq_store_var(b, index, vars->trav.previous_node, nir_imm_int(b, RADV_BVH_INVALID_NODE), 0x1);

41
src/amd/vulkan/radv_rt_common.c
View File

@@ -519,10 +519,8 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
const struct radv_ray_traversal_args *args)
{
nir_variable *incomplete = nir_local_variable_create(b->impl, glsl_bool_type(), "incomplete");
nir_store_var(b, incomplete, nir_ine_imm(b, args->root_bvh_base, 0), 0x1);
nir_store_var(b, incomplete, nir_imm_true(b), 0x1);
nir_push_if(b, nir_load_var(b, incomplete));
{
nir_ssa_def *desc = create_bvh_descriptor(b);
nir_ssa_def *vec3ones = nir_imm_vec3(b, 1.0, 1.0, 1.0);
@@ -533,16 +531,15 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_test_mask(b, args->flags, SpvRayFlagsTerminateOnFirstHitKHRMask),
.no_cull_front = nir_ieq_imm(
b, nir_iand_imm(b, args->flags, SpvRayFlagsCullFrontFacingTrianglesKHRMask), 0),
.no_cull_back = nir_ieq_imm(
b, nir_iand_imm(b, args->flags, SpvRayFlagsCullBackFacingTrianglesKHRMask), 0),
.no_cull_back =
nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullBackFacingTrianglesKHRMask), 0),
.no_cull_opaque =
nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullOpaqueKHRMask), 0),
.no_cull_no_opaque =
nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullNoOpaqueKHRMask), 0),
.no_skip_triangles =
nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsSkipTrianglesKHRMask), 0),
.no_skip_aabbs =
nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsSkipAABBsKHRMask), 0),
.no_skip_aabbs = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsSkipAABBsKHRMask), 0),
};
nir_push_loop(b);
{
@@ -615,8 +612,7 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
}
nir_push_else(b, NULL);
{
nir_store_deref(b, args->vars.previous_node, nir_imm_int(b, RADV_BVH_INVALID_NODE),
0x1);
nir_store_deref(b, args->vars.previous_node, nir_imm_int(b, RADV_BVH_INVALID_NODE), 0x1);
}
nir_pop_if(b, NULL);
@@ -632,9 +628,9 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_ssa_def *intrinsic_result = NULL;
if (!radv_emulate_rt(device->physical_device)) {
intrinsic_result = nir_bvh64_intersect_ray_amd(
b, 32, desc, nir_unpack_64_2x32(b, global_bvh_node),
nir_load_deref(b, args->vars.tmax), nir_load_deref(b, args->vars.origin),
nir_load_deref(b, args->vars.dir), nir_load_deref(b, args->vars.inv_dir));
b, 32, desc, nir_unpack_64_2x32(b, global_bvh_node), nir_load_deref(b, args->vars.tmax),
nir_load_deref(b, args->vars.origin), nir_load_deref(b, args->vars.dir),
nir_load_deref(b, args->vars.inv_dir));
}
nir_ssa_def *node_type = nir_iand_imm(b, bvh_node, 7);
@@ -670,8 +666,7 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_pack_64_2x32(b, nir_channels(b, instance_data, 0x3)), 1);
/* Push the instance root node onto the stack */
nir_store_deref(b, args->vars.current_node, nir_imm_int(b, RADV_BVH_ROOT_NODE),
0x1);
nir_store_deref(b, args->vars.current_node, nir_imm_int(b, RADV_BVH_ROOT_NODE), 0x1);
nir_store_deref(b, args->vars.instance_bottom_node,
nir_imm_int(b, RADV_BVH_ROOT_NODE), 1);
nir_store_deref(b, args->vars.instance_top_node, bvh_node, 1);
@@ -684,8 +679,8 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_store_deref(b, args->vars.inv_dir,
nir_fdiv(b, vec3ones, nir_load_deref(b, args->vars.dir)), 7);
nir_store_deref(b, args->vars.sbt_offset_and_flags,
nir_channel(b, instance_data, 3), 1);
nir_store_deref(b, args->vars.sbt_offset_and_flags, nir_channel(b, instance_data, 3),
1);
nir_store_deref(b, args->vars.instance_addr, instance_node_addr, 1);
}
nir_pop_if(b, NULL);
@@ -714,18 +709,18 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
for (unsigned i = 4; i-- > 1;) {
nir_ssa_def *stack = nir_load_deref(b, args->vars.stack);
nir_ssa_def *stack_ptr = nir_umod(
b, stack, nir_imm_int(b, args->stack_entries * args->stack_stride));
nir_ssa_def *stack_ptr =
nir_umod(b, stack, nir_imm_int(b, args->stack_entries * args->stack_stride));
args->stack_store_cb(b, stack_ptr, new_nodes[i], args);
nir_store_deref(b, args->vars.stack,
nir_iadd_imm(b, stack, args->stack_stride), 1);
nir_store_deref(b, args->vars.stack, nir_iadd_imm(b, stack, args->stack_stride),
1);
if (i == 1) {
nir_ssa_def *new_watermark =
nir_iadd_imm(b, nir_load_deref(b, args->vars.stack),
-args->stack_entries * args->stack_stride);
new_watermark = nir_imax(
b, nir_load_deref(b, args->vars.stack_low_watermark), new_watermark);
new_watermark = nir_imax(b, nir_load_deref(b, args->vars.stack_low_watermark),
new_watermark);
nir_store_deref(b, args->vars.stack_low_watermark, new_watermark, 0x1);
}
@@ -762,8 +757,6 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_pop_if(b, NULL);
}
nir_pop_loop(b, NULL);
}
nir_pop_if(b, NULL);
return nir_load_var(b, incomplete);
}

7
src/amd/vulkan/radv_rt_shader.c
View File

@@ -1333,8 +1333,6 @@ build_traversal_shader(struct radv_device *device,
nir_store_var(&b, trav_vars.hit, nir_imm_false(&b), 1);
nir_push_if(&b, nir_ine_imm(&b, accel_struct, 0));
{
nir_ssa_def *bvh_offset = nir_build_load_global(
&b, 1, 32,
nir_iadd_imm(&b, accel_struct, offsetof(struct radv_accel_struct_header, bvh_offset)),
@@ -1348,8 +1346,7 @@ build_traversal_shader(struct radv_device *device,
nir_store_var(&b, trav_vars.origin, nir_load_var(&b, vars.origin), 7);
nir_store_var(&b, trav_vars.dir, nir_load_var(&b, vars.direction), 7);
nir_store_var(&b, trav_vars.inv_dir, nir_fdiv(&b, vec3ones, nir_load_var(&b, trav_vars.dir)),
7);
nir_store_var(&b, trav_vars.inv_dir, nir_fdiv(&b, vec3ones, nir_load_var(&b, trav_vars.dir)), 7);
nir_store_var(&b, trav_vars.sbt_offset_and_flags, nir_imm_int(&b, 0), 1);
nir_store_var(&b, trav_vars.instance_addr, nir_imm_int64(&b, 0), 1);
@@ -1412,8 +1409,6 @@ build_traversal_shader(struct radv_device *device,
};
radv_build_ray_traversal(device, &b, &args);
}
nir_pop_if(&b, NULL);
/* Initialize follow-up shader. */
nir_push_if(&b, nir_load_var(&b, trav_vars.hit));