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intel: compiler/i965: fix is_broxton checks

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In 5f2fe9302c is_geminilake was introduced for the differenciate
broxton from geminilake. Unfortunately I failed as verifying that
is_broxton is throughout the code base to mean Gen9lp.

Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Lionel Landwerlin
2017-06-20 11:06:24 +01:00
parent b3b6121115
commit 030abc6109
6 changed files with 10 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/intel/common/gen_device_info.h
View File

@@ -186,6 +186,9 @@ struct gen_device_info
/** @} */
};
#define gen_device_info_is_9lp(devinfo) \
(devinfo->is_broxton || devinfo->is_geminilake)
bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
const char *gen_get_device_name(int devid);

2
src/intel/compiler/brw_fs.cpp
View File

@@ -3348,7 +3348,7 @@ fs_visitor::lower_integer_multiplication()
* operation directly, but CHV/BXT cannot.
*/
if (devinfo->gen >= 8 &&
!devinfo->is_cherryview && !devinfo->is_broxton)
!devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo))
continue;
if (inst->src[1].file == IMM &&

4
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -639,7 +639,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
*/
if (nir_dest_bit_size(instr->dest.dest) == 64 &&
nir_src_bit_size(instr->src[0].src) == 32 &&
(devinfo->is_cherryview || devinfo->is_broxton)) {
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
fs_reg tmp = bld.vgrf(result.type, 1);
tmp = subscript(tmp, op[0].type, 0);
inst = bld.MOV(tmp, op[0]);
@@ -3748,7 +3748,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
(instr->num_components - 1) * type_sz(dest.type);
bool supports_64bit_indirects =
!devinfo->is_cherryview && !devinfo->is_broxton;
!devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo);
if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
for (unsigned j = 0; j < instr->num_components; j++) {

2
src/intel/compiler/brw_vec4.cpp
View File

@@ -985,7 +985,7 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
* affected, at least by the 64b restriction, since DepCtrl with double
* precision instructions seems to produce GPU hangs in some cases.
*/
if (devinfo->gen == 8 || devinfo->is_broxton) {
if (devinfo->gen == 8 || gen_device_info_is_9lp(devinfo)) {
if (inst->opcode == BRW_OPCODE_MUL &&
IS_DWORD(inst->src[0]) &&
IS_DWORD(inst->src[1]))

4
src/intel/isl/isl_format.c
View File

@@ -406,7 +406,7 @@ isl_format_supports_sampling(const struct gen_device_info *devinfo,
*/
if (fmtl->txc == ISL_TXC_ASTC)
return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
} else if (devinfo->is_broxton) {
} else if (gen_device_info_is_9lp(devinfo)) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC HDR exists on Broxton even though big-core
* GPUs didn't get it until Cannonlake.
@@ -439,7 +439,7 @@ isl_format_supports_filtering(const struct gen_device_info *devinfo,
*/
if (fmtl->txc == ISL_TXC_ASTC)
return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
} else if (devinfo->is_broxton) {
} else if (gen_device_info_is_9lp(devinfo)) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC HDR exists on Broxton even though big-core
* GPUs didn't get it until Cannonlake.

2
src/mesa/drivers/dri/i965/brw_context.c
View File

@@ -945,7 +945,7 @@ brwCreateContext(gl_api api,
brw->is_baytrail = devinfo->is_baytrail;
brw->is_haswell = devinfo->is_haswell;
brw->is_cherryview = devinfo->is_cherryview;
brw->is_broxton = devinfo->is_broxton;
brw->is_broxton = devinfo->is_broxton || devinfo->is_geminilake;
brw->has_llc = devinfo->has_llc;
brw->has_hiz = devinfo->has_hiz_and_separate_stencil;
brw->has_separate_stencil = devinfo->has_hiz_and_separate_stencil;