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isl, anv, iris: Add a centralized helper to select MOCS based on usage

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On Gen12+, we can enable additional caches in certain usage situations.
This routes that decision making to a central place in ISL, based on
surface usage flags, and updates both drivers to use it.  (i965 doesn't
need to change because it doesn't support Gen12.)

We continue handling the "external" decision via an anv_mocs() wrapper
for now, since we store that flag in anv_bo, which isl doesn't know
about.  (We could introduce an ISL_SURF_USAGE_EXTERNAL, but I'm not
actually sure that would be cleaner.)

This patch should not have any functional nor performance effects, as
we continue selecting the exact same MOCS values for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7104>
This commit is contained in:
Kenneth Graunke
2020-10-07 07:44:56 -07:00
committed by Marge Bot
parent 103ad427bc
commit 02fe825a61
21 changed files with 159 additions and 79 deletions
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8
src/gallium/drivers/iris/iris_blit.c
View File

@@ -250,7 +250,9 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.buffer = res->bo,
.offset = res->offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
.mocs = iris_mocs(res->bo, isl_dev),
.mocs = iris_mocs(res->bo, isl_dev,
is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT),
},
.aux_usage = aux_usage,
};
@@ -261,7 +263,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.buffer = res->aux.bo,
.offset = res->aux.offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
.mocs = iris_mocs(res->bo, isl_dev),
.mocs = iris_mocs(res->bo, isl_dev, 0),
};
surf->clear_color =
iris_resource_get_clear_color(res, NULL, NULL);
@@ -269,7 +271,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.buffer = res->aux.clear_color_bo,
.offset = res->aux.clear_color_offset,
.reloc_flags = 0,
.mocs = iris_mocs(res->aux.clear_color_bo, isl_dev),
.mocs = iris_mocs(res->aux.clear_color_bo, isl_dev, 0),
};
}
}

3
src/gallium/drivers/iris/iris_blorp.c
View File

@@ -183,7 +183,8 @@ blorp_alloc_vertex_buffer(struct blorp_batch *blorp_batch,
*addr = (struct blorp_address) {
.buffer = bo,
.offset = offset,
.mocs = iris_mocs(bo, &batch->screen->isl_dev),
.mocs = iris_mocs(bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT),
};
return map;

2
src/gallium/drivers/iris/iris_context.h
View File

@@ -850,7 +850,7 @@ uint32_t iris_upload_border_color(struct iris_context *ice,
void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
struct pipe_shader_buffer *buf,
struct iris_state_ref *surf_state,
bool ssbo);
isl_surf_usage_flags_t usage);
const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
gl_shader_stage stage);
struct iris_bo *iris_get_scratch_space(struct iris_context *ice,

3
src/gallium/drivers/iris/iris_draw.c
View File

@@ -332,7 +332,8 @@ iris_update_grid_size_resource(struct iris_context *ice,
.size_B = sizeof(grid->grid),
.format = ISL_FORMAT_RAW,
.stride_B = 1,
.mocs = iris_mocs(grid_bo, isl_dev));
.mocs = iris_mocs(grid_bo, isl_dev,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT));
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_CS;
}

8
src/gallium/drivers/iris/iris_program.c
View File

@@ -153,10 +153,11 @@ void
iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
struct pipe_shader_buffer *buf,
struct iris_state_ref *surf_state,
bool ssbo)
isl_surf_usage_flags_t usage)
{
struct pipe_context *ctx = &ice->ctx;
struct iris_screen *screen = (struct iris_screen *) ctx->screen;
bool ssbo = usage & ISL_SURF_USAGE_STORAGE_BIT;
void *map =
upload_state(ice->state.surface_uploader, surf_state,
@@ -178,7 +179,7 @@ iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
: ISL_FORMAT_R32G32B32A32_FLOAT,
.swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = 1,
.mocs = iris_mocs(res->bo, &screen->isl_dev));
.mocs = iris_mocs(res->bo, &screen->isl_dev, usage));
}
static nir_ssa_def *
@@ -1833,7 +1834,8 @@ iris_update_pull_constant_descriptors(struct iris_context *ice,
struct pipe_shader_buffer *cbuf = &shs->constbuf[i];
struct iris_state_ref *surf_state = &shs->constbuf_surf_state[i];
if (!surf_state->res && cbuf->buffer) {
iris_upload_ubo_ssbo_surf_state(ice, cbuf, surf_state, false);
iris_upload_ubo_ssbo_surf_state(ice, cbuf, surf_state,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT);
any_new_descriptors = true;
}
}

3
src/gallium/drivers/iris/iris_resource.c
View File

@@ -511,6 +511,9 @@ iris_resource_configure_main(const struct iris_screen *screen,
isl_surf_usage_flags_t usage = 0;
if (templ->usage == PIPE_USAGE_STAGING)
usage |= ISL_SURF_USAGE_STAGING_BIT;
if (templ->bind & PIPE_BIND_RENDER_TARGET)
usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;

6
src/gallium/drivers/iris/iris_resource.h
View File

@@ -292,9 +292,11 @@ iris_resource_bo(struct pipe_resource *p_res)
}
static inline uint32_t
iris_mocs(const struct iris_bo *bo, const struct isl_device *dev)
iris_mocs(const struct iris_bo *bo,
const struct isl_device *dev,
isl_surf_usage_flags_t usage)
{
return bo && bo->external ? dev->mocs.external : dev->mocs.internal;
return bo && bo->external ? dev->mocs.external : isl_mocs(dev, usage);
}
struct iris_format_info iris_format_for_usage(const struct gen_device_info *,

54
src/gallium/drivers/iris/iris_state.c
View File

@@ -697,7 +697,8 @@ init_glk_barrier_mode(struct iris_batch *batch, uint32_t value)
static void
init_state_base_address(struct iris_batch *batch)
{
uint32_t mocs = batch->screen->isl_dev.mocs.internal;
struct isl_device *isl_dev = &batch->screen->isl_dev;
uint32_t mocs = isl_mocs(isl_dev, 0);
flush_before_state_base_change(batch);
/* We program most base addresses once at context initialization time.
@@ -2145,7 +2146,8 @@ fill_buffer_surface_state(struct isl_device *isl_dev,
enum isl_format format,
struct isl_swizzle swizzle,
unsigned offset,
unsigned size)
unsigned size,
isl_surf_usage_flags_t usage)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
const unsigned cpp = format == ISL_FORMAT_RAW ? 1 : fmtl->bpb / 8;
@@ -2176,7 +2178,7 @@ fill_buffer_surface_state(struct isl_device *isl_dev,
.format = format,
.swizzle = swizzle,
.stride_B = cpp,
.mocs = iris_mocs(res->bo, isl_dev));
.mocs = iris_mocs(res->bo, isl_dev, usage));
}
#define SURFACE_STATE_ALIGNMENT 64
@@ -2335,7 +2337,7 @@ fill_surface_state(struct isl_device *isl_dev,
struct isl_surf_fill_state_info f = {
.surf = surf,
.view = view,
.mocs = iris_mocs(res->bo, isl_dev),
.mocs = iris_mocs(res->bo, isl_dev, view->usage),
.address = res->bo->gtt_offset + res->offset + extra_main_offset,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa,
@@ -2451,7 +2453,8 @@ iris_create_sampler_view(struct pipe_context *ctx,
} else {
fill_buffer_surface_state(&screen->isl_dev, isv->res, map,
isv->view.format, isv->view.swizzle,
tmpl->u.buf.offset, tmpl->u.buf.size);
tmpl->u.buf.offset, tmpl->u.buf.size,
ISL_SURF_USAGE_TEXTURE_BIT);
}
upload_surface_states(ice->state.surface_uploader, &isv->surface_state);
@@ -2677,7 +2680,8 @@ iris_create_surface(struct pipe_context *ctx,
struct isl_surf_fill_state_info f = {
.surf = &isl_surf,
.view = view,
.mocs = iris_mocs(res->bo, &screen->isl_dev),
.mocs = iris_mocs(res->bo, &screen->isl_dev,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
.address = res->bo->gtt_offset + offset_B,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa,
@@ -2780,7 +2784,8 @@ iris_set_shader_images(struct pipe_context *ctx,
if (isl_fmt == ISL_FORMAT_RAW) {
fill_buffer_surface_state(&screen->isl_dev, res, map,
isl_fmt, ISL_SWIZZLE_IDENTITY,
0, res->bo->size);
0, res->bo->size,
ISL_SURF_USAGE_STORAGE_BIT);
} else {
unsigned aux_modes = aux_usages;
while (aux_modes) {
@@ -2802,7 +2807,8 @@ iris_set_shader_images(struct pipe_context *ctx,
fill_buffer_surface_state(&screen->isl_dev, res, map,
isl_fmt, ISL_SWIZZLE_IDENTITY,
img->u.buf.offset, img->u.buf.size);
img->u.buf.offset, img->u.buf.size,
ISL_SURF_USAGE_STORAGE_BIT);
fill_buffer_image_param(&image_params[start_slot + i],
img->format, img->u.buf.size);
}
@@ -3132,7 +3138,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
info.depth_surf = &zres->surf;
info.depth_address = zres->bo->gtt_offset + zres->offset;
info.mocs = iris_mocs(zres->bo, isl_dev);
info.mocs = iris_mocs(zres->bo, isl_dev, view.usage);
view.format = zres->surf.format;
@@ -3150,7 +3156,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset;
if (!zres) {
view.format = stencil_res->surf.format;
info.mocs = iris_mocs(stencil_res->bo, isl_dev);
info.mocs = iris_mocs(stencil_res->bo, isl_dev, view.usage);
}
}
}
@@ -3325,7 +3331,8 @@ upload_sysvals(struct iris_context *ice,
cbuf->buffer_size = upload_size;
iris_upload_ubo_ssbo_surf_state(ice, cbuf,
&shs->constbuf_surf_state[sysval_cbuf_index], false);
&shs->constbuf_surf_state[sysval_cbuf_index],
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT);
shs->sysvals_need_upload = false;
}
@@ -3366,7 +3373,9 @@ iris_set_shader_buffers(struct pipe_context *ctx,
shs->bound_ssbos |= 1 << (start_slot + i);
iris_upload_ubo_ssbo_surf_state(ice, ssbo, surf_state, true);
isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
iris_upload_ubo_ssbo_surf_state(ice, ssbo, surf_state, usage);
res->bind_history |= PIPE_BIND_SHADER_BUFFER;
res->bind_stages |= 1 << stage;
@@ -3436,7 +3445,8 @@ iris_set_vertex_buffers(struct pipe_context *ctx,
vb.BufferSize = res->base.width0 - (int) buffer->buffer_offset;
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
vb.MOCS = iris_mocs(res->bo, &screen->isl_dev);
vb.MOCS = iris_mocs(res->bo, &screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT);
} else {
vb.NullVertexBuffer = true;
}
@@ -3739,7 +3749,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
sob.SOBufferEnable = true;
sob.StreamOffsetWriteEnable = true;
sob.StreamOutputBufferOffsetAddressEnable = true;
sob.MOCS = iris_mocs(res->bo, &screen->isl_dev);
sob.MOCS = iris_mocs(res->bo, &screen->isl_dev, 0);
sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
sob.StreamOffset = offset;
@@ -5183,7 +5193,8 @@ iris_update_surface_base_address(struct iris_batch *batch,
if (batch->last_surface_base_address == binder->bo->gtt_offset)
return;
uint32_t mocs = batch->screen->isl_dev.mocs.internal;
struct isl_device *isl_dev = &batch->screen->isl_dev;
uint32_t mocs = isl_mocs(isl_dev, 0);
iris_batch_sync_region_start(batch);
@@ -5364,7 +5375,7 @@ emit_push_constant_packets(struct iris_context *ice,
iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
#if GEN_GEN >= 12
pkt.MOCS = isl_dev->mocs.internal;
pkt.MOCS = isl_mocs(isl_dev, 0);
#endif
if (prog_data) {
/* The Skylake PRM contains the following restriction:
@@ -5415,7 +5426,7 @@ emit_push_constant_packet_all(struct iris_context *ice,
assert(n <= max_pointers);
iris_pack_command(GENX(3DSTATE_CONSTANT_ALL), dw, all) {
all.DWordLength = num_dwords - 2;
all.MOCS = isl_dev->mocs.internal;
all.MOCS = isl_mocs(isl_dev, 0);
all.ShaderUpdateEnable = shader_mask;
all.PointerBufferMask = (1 << n) - 1;
}
@@ -6159,7 +6170,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.draw_params.offset);
vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev);
vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT);
}
dynamic_bound |= 1ull << count;
count++;
@@ -6181,7 +6193,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.derived_draw_params.offset);
vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev);
vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT);
}
dynamic_bound |= 1ull << count;
count++;
@@ -6440,7 +6453,8 @@ iris_upload_render_state(struct iris_context *ice,
uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)];
iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) {
ib.IndexFormat = draw->index_size >> 1;
ib.MOCS = iris_mocs(bo, &batch->screen->isl_dev);
ib.MOCS = iris_mocs(bo, &batch->screen->isl_dev,
ISL_SURF_USAGE_INDEX_BUFFER_BIT);
ib.BufferSize = bo->size - offset;
ib.BufferStartingAddress = ro_bo(NULL, bo->gtt_offset + offset);
}

9
src/intel/isl/isl.c
View File

@@ -154,6 +154,15 @@ isl_device_setup_mocs(struct isl_device *dev)
}
}
/**
* Return an appropriate MOCS entry for the given usage flags.
*/
uint32_t
isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage)
{
return dev->mocs.internal;
}
void
isl_device_init(struct isl_device *dev,
const struct gen_device_info *info,

6
src/intel/isl/isl.h
View File

@@ -917,6 +917,10 @@ typedef uint64_t isl_surf_usage_flags_t;
#define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
#define ISL_SURF_USAGE_MCS_BIT (1u << 14)
#define ISL_SURF_USAGE_CCS_BIT (1u << 15)
#define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 16)
#define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 17)
#define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 18)
#define ISL_SURF_USAGE_STAGING_BIT (1u << 19)
/** @} */
/**
@@ -1996,6 +2000,8 @@ isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
struct isl_swizzle
isl_swizzle_invert(struct isl_swizzle swizzle);
uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage);
#define isl_surf_init(dev, surf, ...) \
isl_surf_init_s((dev), (surf), \
&(struct isl_surf_init_info) { __VA_ARGS__ });

36
src/intel/vulkan/anv_blorp.c
View File

@@ -158,7 +158,9 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
.addr = {
.buffer = buffer->address.bo,
.offset = buffer->address.offset + offset,
.mocs = anv_mocs_for_bo(device, buffer->address.bo),
.mocs = anv_mocs(device, buffer->address.bo,
is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT),
},
};
@@ -209,13 +211,17 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
aspect, usage, layout);
}
isl_surf_usage_flags_t mocs_usage =
(usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) ?
ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
const struct anv_surface *surface = &image->planes[plane].surface;
*blorp_surf = (struct blorp_surf) {
.surf = &surface->isl,
.addr = {
.buffer = image->planes[plane].address.bo,
.offset = image->planes[plane].address.offset + surface->offset,
.mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo),
.mocs = anv_mocs(device, image->planes[plane].address.bo, mocs_usage),
},
};
@@ -225,7 +231,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
blorp_surf->aux_addr = (struct blorp_address) {
.buffer = image->planes[plane].address.bo,
.offset = image->planes[plane].address.offset + aux_surface->offset,
.mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo),
.mocs = anv_mocs(device, image->planes[plane].address.bo, 0),
};
blorp_surf->aux_usage = aux_usage;
@@ -277,7 +283,8 @@ get_blorp_surf_for_anv_shadow_image(const struct anv_device *device,
.buffer = image->planes[plane].address.bo,
.offset = image->planes[plane].address.offset +
image->planes[plane].shadow_surface.offset,
.mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo),
.mocs = anv_mocs(device, image->planes[plane].address.bo,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
},
};
@@ -948,12 +955,14 @@ copy_buffer(struct anv_device *device,
struct blorp_address src = {
.buffer = src_buffer->address.bo,
.offset = src_buffer->address.offset + region->srcOffset,
.mocs = anv_mocs_for_bo(device, src_buffer->address.bo),
.mocs = anv_mocs(device, src_buffer->address.bo,
ISL_SURF_USAGE_TEXTURE_BIT),
};
struct blorp_address dst = {
.buffer = dst_buffer->address.bo,
.offset = dst_buffer->address.offset + region->dstOffset,
.mocs = anv_mocs_for_bo(device, dst_buffer->address.bo),
.mocs = anv_mocs(device, dst_buffer->address.bo,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
};
blorp_buffer_copy(batch, src, dst, region->size);
@@ -1048,12 +1057,14 @@ void anv_CmdUpdateBuffer(
struct blorp_address src = {
.buffer = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = tmp_data.offset,
.mocs = cmd_buffer->device->isl_dev.mocs.internal,
.mocs = isl_mocs(&cmd_buffer->device->isl_dev,
ISL_SURF_USAGE_TEXTURE_BIT)
};
struct blorp_address dst = {
.buffer = dst_buffer->address.bo,
.offset = dst_buffer->address.offset + dstOffset,
.mocs = anv_mocs_for_bo(cmd_buffer->device, dst_buffer->address.bo),
.mocs = anv_mocs(cmd_buffer->device, dst_buffer->address.bo,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
};
blorp_buffer_copy(&batch, src, dst, copy_size);
@@ -1553,7 +1564,8 @@ anv_image_msaa_resolve(struct anv_cmd_buffer *cmd_buffer,
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, aspect,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
src_aux_usage, &src_surf);
if (src_aux_usage == ISL_AUX_USAGE_MCS) {
src_surf.clear_color_addr = anv_to_blorp_address(
@@ -1561,7 +1573,8 @@ anv_image_msaa_resolve(struct anv_cmd_buffer *cmd_buffer,
VK_IMAGE_ASPECT_COLOR_BIT));
}
get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, aspect,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
dst_aux_usage, &dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
aspect, dst_aux_usage,
@@ -1769,7 +1782,8 @@ anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
VK_IMAGE_USAGE_TRANSFER_DST_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
aux_usage, &surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, image, aspect, aux_usage,
level, base_layer, layer_count);

1
src/intel/vulkan/anv_cmd_buffer.c
View File

@@ -1275,6 +1275,7 @@ anv_cmd_buffer_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
isl_dev->ss.size, isl_dev->ss.align);
anv_fill_buffer_surface_state(cmd_buffer->device,
set->desc_surface_state, format,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT,
addr, layout->descriptor_buffer_size, 1);
}

10
src/intel/vulkan/anv_descriptor_set.c
View File

@@ -1085,6 +1085,7 @@ anv_descriptor_set_create(struct anv_device *device,
set->desc_surface_state = anv_descriptor_pool_alloc_state(pool);
anv_fill_buffer_surface_state(device, set->desc_surface_state, format,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT,
(struct anv_address) {
.bo = pool->bo,
.offset = set->desc_mem.offset,
@@ -1508,8 +1509,15 @@ anv_descriptor_set_write_buffer(struct anv_device *device,
if (alloc_stream)
bview->surface_state = anv_state_stream_alloc(alloc_stream, 64, 64);
isl_surf_usage_flags_t usage =
(type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER ||
type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC) ?
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT :
ISL_SURF_USAGE_STORAGE_BIT;
anv_fill_buffer_surface_state(device, bview->surface_state,
bview->format, bind_addr, bind_range, 1);
bview->format, usage,
bind_addr, bind_range, 1);
*desc = (struct anv_descriptor) {
.type = type,

3
src/intel/vulkan/anv_device.c
View File

@@ -4341,12 +4341,13 @@ uint64_t anv_GetDeviceMemoryOpaqueCaptureAddress(
void
anv_fill_buffer_surface_state(struct anv_device *device, struct anv_state state,
enum isl_format format,
isl_surf_usage_flags_t usage,
struct anv_address address,
uint32_t range, uint32_t stride)
{
isl_buffer_fill_state(&device->isl_dev, state.map,
.address = anv_address_physical(address),
.mocs = device->isl_dev.mocs.internal,
.mocs = isl_mocs(&device->isl_dev, usage),
.size_B = range,
.format = format,
.swizzle = ISL_SWIZZLE_IDENTITY,

12
src/intel/vulkan/anv_image.c
View File

@@ -1754,7 +1754,7 @@ anv_image_fill_surface_state(struct anv_device *device,
.format = ISL_FORMAT_RAW,
.swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = 1,
.mocs = anv_mocs_for_bo(device, address.bo));
.mocs = anv_mocs(device, address.bo, view_usage));
state_inout->address = address,
state_inout->aux_address = ANV_NULL_ADDRESS;
state_inout->clear_address = ANV_NULL_ADDRESS;
@@ -1852,8 +1852,8 @@ anv_image_fill_surface_state(struct anv_device *device,
.aux_address = anv_address_physical(aux_address),
.clear_address = anv_address_physical(clear_address),
.use_clear_address = !anv_address_is_null(clear_address),
.mocs = anv_mocs_for_bo(device,
state_inout->address.bo),
.mocs = anv_mocs(device, state_inout->address.bo,
view_usage),
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa);
@@ -2226,7 +2226,7 @@ anv_CreateBufferView(VkDevice _device,
view->surface_state = alloc_surface_state(device);
anv_fill_buffer_surface_state(device, view->surface_state,
view->format,
view->format, ISL_SURF_USAGE_TEXTURE_BIT,
view->address, view->range, format_bs);
} else {
view->surface_state = (struct anv_state){ 0 };
@@ -2243,14 +2243,14 @@ anv_CreateBufferView(VkDevice _device,
ISL_FORMAT_RAW;
anv_fill_buffer_surface_state(device, view->storage_surface_state,
storage_format,
storage_format, ISL_SURF_USAGE_STORAGE_BIT,
view->address, view->range,
(storage_format == ISL_FORMAT_RAW ? 1 :
isl_format_get_layout(storage_format)->bpb / 8));
/* Write-only accesses should use the original format. */
anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
view->format,
view->format, ISL_SURF_USAGE_STORAGE_BIT,
view->address, view->range,
isl_format_get_layout(view->format)->bpb / 8);

9
src/intel/vulkan/anv_private.h
View File

@@ -1453,12 +1453,14 @@ anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
}
static inline uint32_t
anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
anv_mocs(const struct anv_device *device,
const struct anv_bo *bo,
isl_surf_usage_flags_t usage)
{
if (bo->is_external)
return device->isl_dev.mocs.external;
else
return device->isl_dev.mocs.internal;
return isl_mocs(&device->isl_dev, usage);
}
void anv_device_init_blorp(struct anv_device *device);
@@ -4257,6 +4259,7 @@ anv_get_image_format_features(const struct gen_device_info *devinfo,
void anv_fill_buffer_surface_state(struct anv_device *device,
struct anv_state state,
enum isl_format format,
isl_surf_usage_flags_t usage,
struct anv_address address,
uint32_t range, uint32_t stride);

16
src/intel/vulkan/gen7_cmd_buffer.c
View File

@@ -313,16 +313,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if !GEN_IS_HASWELL
ib.CutIndexEnable = pipeline->primitive_restart;
ib.CutIndexEnable = pipeline->primitive_restart;
#endif
ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;
ib.MOCS = anv_mocs_for_bo(cmd_buffer->device,
buffer->address.bo);
ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;
ib.MOCS = anv_mocs(cmd_buffer->device,
buffer->address.bo,
ISL_SURF_USAGE_INDEX_BUFFER_BIT);
ib.BufferStartingAddress = anv_address_add(buffer->address,
offset);
ib.BufferEndingAddress = anv_address_add(buffer->address,
buffer->size);
ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
ib.BufferEndingAddress = anv_address_add(buffer->address,
buffer->size);
}
}

11
src/intel/vulkan/gen8_cmd_buffer.c
View File

@@ -691,11 +691,12 @@ void genX(CmdBindIndexBuffer)(
cmd_buffer->state.restart_index = restart_index_for_type(indexType);
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
ib.IndexFormat = vk_to_gen_index_type(indexType);
ib.MOCS = anv_mocs_for_bo(cmd_buffer->device,
buffer->address.bo);
ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
ib.BufferSize = buffer->size - offset;
ib.IndexFormat = vk_to_gen_index_type(indexType);
ib.MOCS = anv_mocs(cmd_buffer->device,
buffer->address.bo,
ISL_SURF_USAGE_INDEX_BUFFER_BIT);
ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
ib.BufferSize = buffer->size - offset;
}
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;

3
src/intel/vulkan/genX_blorp_exec.c
View File

@@ -145,7 +145,8 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
*addr = (struct blorp_address) {
.buffer = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = vb_state.offset,
.mocs = cmd_buffer->device->isl_dev.mocs.internal,
.mocs = isl_mocs(&cmd_buffer->device->isl_dev,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT),
};
return vb_state.map;

31
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -60,7 +60,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
UNUSED const struct gen_device_info *devinfo = &device->info;
uint32_t mocs = device->isl_dev.mocs.internal;
uint32_t mocs = isl_mocs(&device->isl_dev, 0);
/* If we are emitting a new state base address we probably need to re-emit
* binding tables.
@@ -2552,6 +2552,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER);
anv_fill_buffer_surface_state(cmd_buffer->device,
surface_state, format,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT,
constant_data, constant_data_size, 1);
assert(surface_state.map);
@@ -2572,6 +2573,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
format,
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT,
cmd_buffer->state.compute.num_workgroups,
12, 1);
@@ -2724,8 +2726,13 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
anv_isl_format_for_descriptor_type(cmd_buffer->device,
desc->type);
isl_surf_usage_flags_t usage =
desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ?
ISL_SURF_USAGE_CONSTANT_BUFFER_BIT :
ISL_SURF_USAGE_STORAGE_BIT;
anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
format, address, range, 1);
format, usage, address, range, 1);
if (need_client_mem_relocs)
add_surface_reloc(cmd_buffer, surface_state, address);
} else {
@@ -3096,7 +3103,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
* same bit of memory for both scanout and a UBO is nuts. Let's not
* bother and assume it's all internal.
*/
c.MOCS = cmd_buffer->device->isl_dev.mocs.internal;
c.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0);
#endif
#if GEN_GEN >= 8 || GEN_IS_HASWELL
@@ -3160,7 +3167,7 @@ cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer,
if (buffer_count == 0) {
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_ALL), c) {
c.ShaderUpdateEnable = shader_mask;
c.MOCS = cmd_buffer->device->isl_dev.mocs.internal;
c.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0);
}
return;
}
@@ -3192,7 +3199,7 @@ cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer,
GENX(3DSTATE_CONSTANT_ALL),
.ShaderUpdateEnable = shader_mask,
.PointerBufferMask = buffer_mask,
.MOCS = cmd_buffer->device->isl_dev.mocs.internal);
.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0));
for (int i = 0; i < buffer_count; i++) {
const struct anv_push_range *range = &bind_map->push_ranges[i];
@@ -3417,7 +3424,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
state = (struct GENX(VERTEX_BUFFER_STATE)) {
.VertexBufferIndex = vb,
.MOCS = anv_mocs_for_bo(cmd_buffer->device, buffer->address.bo),
.MOCS = anv_mocs(cmd_buffer->device, buffer->address.bo,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT),
#if GEN_GEN <= 7
.BufferAccessType = pipeline->vb[vb].instanced ? INSTANCEDATA : VERTEXDATA,
.InstanceDataStepRate = pipeline->vb[vb].instance_divisor,
@@ -3470,7 +3478,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
#endif
if (cmd_buffer->state.xfb_enabled && xfb->buffer && xfb->size != 0) {
sob.MOCS = cmd_buffer->device->isl_dev.mocs.internal,
sob.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0);
sob.SurfaceBaseAddress = anv_address_add(xfb->buffer->address,
xfb->offset);
#if GEN_GEN >= 8
@@ -3591,7 +3599,8 @@ emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
.VertexBufferIndex = index,
.AddressModifyEnable = true,
.BufferPitch = 0,
.MOCS = addr.bo ? anv_mocs_for_bo(cmd_buffer->device, addr.bo) : 0,
.MOCS = addr.bo ? anv_mocs(cmd_buffer->device, addr.bo,
ISL_SURF_USAGE_VERTEX_BUFFER_BIT) : 0,
.NullVertexBuffer = size == 0,
#if (GEN_GEN >= 8)
.BufferStartingAddress = addr,
@@ -5024,7 +5033,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
image->planes[depth_plane].address.offset +
surface->offset);
info.mocs =
anv_mocs_for_bo(device, image->planes[depth_plane].address.bo);
anv_mocs(device, image->planes[depth_plane].address.bo,
ISL_SURF_USAGE_DEPTH_BIT);
const uint32_t ds =
cmd_buffer->state.subpass->depth_stencil_attachment->attachment;
@@ -5058,7 +5068,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
image->planes[stencil_plane].address.offset +
surface->offset);
info.mocs =
anv_mocs_for_bo(device, image->planes[stencil_plane].address.bo);
anv_mocs(device, image->planes[stencil_plane].address.bo,
ISL_SURF_USAGE_STENCIL_BIT);
}
isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);

4
src/intel/vulkan/genX_gpu_memcpy.c
View File

@@ -91,7 +91,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
.AddressModifyEnable = true,
.BufferStartingAddress = src,
.BufferPitch = bs,
.MOCS = anv_mocs_for_bo(cmd_buffer->device, src.bo),
.MOCS = anv_mocs(cmd_buffer->device, src.bo, 0),
#if (GEN_GEN >= 8)
.BufferSize = size,
#else
@@ -163,7 +163,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
sob._3DCommandOpcode = 0;
sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD;
#endif
sob.MOCS = anv_mocs_for_bo(cmd_buffer->device, dst.bo),
sob.MOCS = anv_mocs(cmd_buffer->device, dst.bo, 0),
sob.SurfaceBaseAddress = dst;
#if GEN_GEN >= 8