anv: expose a couple of emit helper to build utrace buffer copies
We'll want to copy timestamp buffers when commands buffers are resubmitted multiple times. v2: Merge a couple of #if GFX_VER >= 8 (Rohan) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rohan Garg <rohan.garg@intel.com> Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996>
This commit is contained in:
Lionel Landwerlin
committed by
Marge Bot
Marge Bot
parent
246e2c74d3
commit
02a4d622ed
@@ -51,90 +51,27 @@ gcd_pow2_u64(uint64_t a, uint64_t b)
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return 1 << MIN2(a_log2, b_log2);
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}
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void
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genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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static void
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emit_common_so_memcpy(struct anv_batch *batch, struct anv_device *device,
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const struct intel_l3_config *l3_config)
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{
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if (size == 0)
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return;
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/* The maximum copy block size is 4 32-bit components at a time. */
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assert(size % 4 == 0);
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unsigned bs = gcd_pow2_u64(16, size);
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enum isl_format format;
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switch (bs) {
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case 4: format = ISL_FORMAT_R32_UINT; break;
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case 8: format = ISL_FORMAT_R32G32_UINT; break;
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case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;
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default:
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unreachable("Invalid size");
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}
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if (!cmd_buffer->state.current_l3_config) {
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const struct intel_l3_config *cfg =
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intel_get_default_l3_config(&cmd_buffer->device->info);
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genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
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}
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genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size);
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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uint32_t *dw;
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dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
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GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
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&(struct GENX(VERTEX_BUFFER_STATE)) {
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.VertexBufferIndex = 32, /* Reserved for this */
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.AddressModifyEnable = true,
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.BufferStartingAddress = src,
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.BufferPitch = bs,
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.MOCS = anv_mocs(cmd_buffer->device, src.bo, 0),
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#if GFX_VER >= 12
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.L3BypassDisable = true,
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#endif
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#if (GFX_VER >= 8)
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.BufferSize = size,
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#else
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.EndAddress = anv_address_add(src, size - 1),
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#endif
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});
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dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
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GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
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&(struct GENX(VERTEX_ELEMENT_STATE)) {
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.VertexBufferIndex = 32,
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.Valid = true,
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.SourceElementFormat = format,
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.SourceElementOffset = 0,
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.Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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});
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#if GFX_VER >= 8
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
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anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
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vfi.InstancingEnable = false;
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vfi.VertexElementIndex = 0;
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}
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#endif
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#if GFX_VER >= 8
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);
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anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs);
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#endif
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/* Disable all shader stages */
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TE), te);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_GS), gs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PS), gs);
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anv_batch_emit(batch, GENX(3DSTATE_VS), vs);
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anv_batch_emit(batch, GENX(3DSTATE_HS), hs);
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anv_batch_emit(batch, GENX(3DSTATE_TE), te);
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anv_batch_emit(batch, GENX(3DSTATE_DS), DS);
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anv_batch_emit(batch, GENX(3DSTATE_GS), gs);
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anv_batch_emit(batch, GENX(3DSTATE_PS), gs);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SBE), sbe) {
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anv_batch_emit(batch, GENX(3DSTATE_SBE), sbe) {
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sbe.VertexURBEntryReadOffset = 1;
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sbe.NumberofSFOutputAttributes = 1;
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sbe.VertexURBEntryReadLength = 1;
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@@ -155,18 +92,84 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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*/
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const unsigned entry_size[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };
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genX(emit_urb_setup)(cmd_buffer->device, &cmd_buffer->batch,
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cmd_buffer->state.current_l3_config,
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genX(emit_urb_setup)(device, batch, l3_config,
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VK_SHADER_STAGE_VERTEX_BIT, entry_size, NULL);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
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#if GFX_VER >= 12
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/* Disable Primitive Replication. */
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anv_batch_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
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#endif
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#if GFX_VER >= 8
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anv_batch_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
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topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;
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}
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf) {
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vf.StatisticsEnable = false;
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}
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}
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static void
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emit_so_memcpy(struct anv_batch *batch, struct anv_device *device,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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{
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/* The maximum copy block size is 4 32-bit components at a time. */
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assert(size % 4 == 0);
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unsigned bs = gcd_pow2_u64(16, size);
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enum isl_format format;
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switch (bs) {
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case 4: format = ISL_FORMAT_R32_UINT; break;
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case 8: format = ISL_FORMAT_R32G32_UINT; break;
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case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;
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default:
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unreachable("Invalid size");
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}
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uint32_t *dw;
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dw = anv_batch_emitn(batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
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GENX(VERTEX_BUFFER_STATE_pack)(batch, dw + 1,
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&(struct GENX(VERTEX_BUFFER_STATE)) {
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.VertexBufferIndex = 32, /* Reserved for this */
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.AddressModifyEnable = true,
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.BufferStartingAddress = src,
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.BufferPitch = bs,
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.MOCS = anv_mocs(device, src.bo, 0),
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#if GFX_VER >= 12
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.L3BypassDisable = true,
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#endif
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#if (GFX_VER >= 8)
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.BufferSize = size,
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#else
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.EndAddress = anv_address_add(src, size - 1),
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#endif
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});
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dw = anv_batch_emitn(batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
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GENX(VERTEX_ELEMENT_STATE_pack)(batch, dw + 1,
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&(struct GENX(VERTEX_ELEMENT_STATE)) {
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.VertexBufferIndex = 32,
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.Valid = true,
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.SourceElementFormat = format,
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.SourceElementOffset = 0,
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.Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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});
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anv_batch_emit(batch, GENX(3DSTATE_SO_BUFFER), sob) {
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#if GFX_VER < 12
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sob.SOBufferIndex = 0;
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#else
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sob._3DCommandOpcode = 0;
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sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD;
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#endif
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sob.MOCS = anv_mocs(cmd_buffer->device, dst.bo, 0),
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sob.MOCS = anv_mocs(device, dst.bo, 0),
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sob.SurfaceBaseAddress = dst;
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#if GFX_VER >= 8
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@@ -190,16 +193,16 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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#if GFX_VER <= 7
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/* The hardware can do this for us on BDW+ (see above) */
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {
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anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), load) {
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load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num);
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load.DataDWord = 0;
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}
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#endif
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dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_SO_DECL_LIST),
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dw = anv_batch_emitn(batch, 5, GENX(3DSTATE_SO_DECL_LIST),
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.StreamtoBufferSelects0 = (1 << 0),
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.NumEntries0 = 1);
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GENX(SO_DECL_ENTRY_pack)(&cmd_buffer->batch, dw + 3,
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GENX(SO_DECL_ENTRY_pack)(batch, dw + 3,
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&(struct GENX(SO_DECL_ENTRY)) {
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.Stream0Decl = {
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.OutputBufferSlot = 0,
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@@ -208,7 +211,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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},
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});
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STREAMOUT), so) {
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anv_batch_emit(batch, GENX(3DSTATE_STREAMOUT), so) {
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so.SOFunctionEnable = true;
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so.RenderingDisable = true;
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so.Stream0VertexReadOffset = 0;
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@@ -220,22 +223,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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#endif
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}
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#if GFX_VER >= 8
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
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topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;
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}
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#endif
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_STATISTICS), vf) {
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vf.StatisticsEnable = false;
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}
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#if GFX_VER >= 12
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/* Disable Primitive Replication. */
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
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#endif
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anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
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anv_batch_emit(batch, GENX(3DPRIMITIVE), prim) {
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prim.VertexAccessType = SEQUENTIAL;
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prim.PrimitiveTopologyType = _3DPRIM_POINTLIST;
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prim.VertexCountPerInstance = size / bs;
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@@ -244,6 +232,85 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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prim.StartInstanceLocation = 0;
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prim.BaseVertexLocation = 0;
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}
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}
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void
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genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,
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struct anv_device *device,
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struct anv_batch *batch)
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{
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memset(state, 0, sizeof(*state));
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state->batch = batch;
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state->device = device;
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const struct intel_l3_config *cfg = intel_get_default_l3_config(&device->info);
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genX(emit_l3_config)(batch, device, cfg);
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anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) {
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#if GFX_VER >= 9
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ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
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ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
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#endif
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ps.PipelineSelection = _3D;
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}
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emit_common_so_memcpy(batch, device, device->l3_config);
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}
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void
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genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
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{
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genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D,
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ANV_PIPE_END_OF_PIPE_SYNC_BIT);
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anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
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if ((state->batch->next - state->batch->start) & 4)
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anv_batch_emit(state->batch, GENX(MI_NOOP), noop);
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}
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void
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genX(emit_so_memcpy)(struct anv_memcpy_state *state,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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{
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if (GFX_VER >= 8 && GFX_VER <= 9 &&
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!anv_use_relocations(state->device->physical) &&
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anv_gfx8_9_vb_cache_range_needs_workaround(&state->vb_bound,
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&state->vb_dirty,
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src, size)) {
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genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_VF_CACHE_INVALIDATE_BIT);
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memset(&state->vb_dirty, 0, sizeof(state->vb_dirty));
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}
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emit_so_memcpy(state->batch, state->device, dst, src, size);
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}
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void
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genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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struct anv_address dst, struct anv_address src,
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uint32_t size)
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{
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if (size == 0)
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return;
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if (!cmd_buffer->state.current_l3_config) {
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const struct intel_l3_config *cfg =
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intel_get_default_l3_config(&cmd_buffer->device->info);
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genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
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}
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genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size);
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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genX(flush_pipeline_select_3d)(cmd_buffer);
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emit_common_so_memcpy(&cmd_buffer->batch, cmd_buffer->device,
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cmd_buffer->state.current_l3_config);
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emit_so_memcpy(&cmd_buffer->batch, cmd_buffer->device, dst, src, size);
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genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL,
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1ull << 32);
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